On May 2, 1:24*am, Thomas Stanka <[email protected]>
wrote:
> On 1 Mai, 21:54, "[email protected]"
>
> <[email protected]> wrote:
> > Ok. I have my design finalized. The fir length would be 64 operating
> > on 32 bit wide word. Now could you please hint me on estimating gate
> > count ?
>
> Is it serial or parallel? Using RAM or FF? Which ASIC technology?
> With tight timing constraints or relaxed timing?
>
> My guess would be 65x32 for storage of input and result and two adders
> size 32 bit.
>
> ASIC gate count is a value gained by guess of numbers multiplied with
> e^n with n being a marketing factor (technical oriented people assume
> n=random(unconstrained) as you can't understand calculation of n if
> you'r not member of a marketing department)
>
> bye Thomas

it will be parallel implementation using RAM and relaxed timing. Any
help is appreciated.

Thanks,
Vijayant