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Old 04-15-2008, 09:23 PM
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Default asic gate count

hi,
i have got xilinx fft IP core from coregen. Is there any way that i
can get asic gate count for this ? Any help / hint is greatly
appreciated.

thanks,
vijayant.
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Old 04-15-2008, 09:29 PM
Mike Treseler
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Default Re: asic gate count

[email protected] wrote:

> i have got xilinx fft IP core from coregen. Is there any way that i
> can get asic gate count for this ? Any help / hint is greatly
> appreciated.


An accurate count requires source code.

-- Mike Treseler
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Old 04-16-2008, 06:25 PM
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Default Re: asic gate count

On Apr 15, 1:23 pm, "[email protected]"
<[email protected]> wrote:
> hi,
> i have got xilinx fft IP core from coregen. Is there any way that i
> can get asic gate count for this ? Any help / hint is greatly
> appreciated.
>
> thanks,
> vijayant.


You aren't going to get a corgen part into an ASIC. Just ain't gonna
happen.

If you build the core into a Xilinx part, then multiply the "marketing
size" of the FPGA by the percentage used, you'll get a number that
will give you an idea of the order of magnitude of an ASIC solution.

G.
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  #4 (permalink)  
Old 04-17-2008, 02:28 AM
Muzaffer Kal
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Default Re: asic gate count

On Wed, 16 Apr 2008 10:25:36 -0700 (PDT), [email protected] wrote:

>On Apr 15, 1:23 pm, "[email protected]"
><[email protected]> wrote:
>> hi,
>> i have got xilinx fft IP core from coregen. Is there any way that i
>> can get asic gate count for this ? Any help / hint is greatly
>> appreciated.
>>
>> thanks,
>> vijayant.

>
>You aren't going to get a corgen part into an ASIC. Just ain't gonna
>happen.


Not necessarily true. It is sometimes possible to buy the RTL from
Xilinx for the coregen part in question. If not, one can always pay
someone (ahem :-) to develop another module which duplicates the
behavior.
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Old 05-03-2008, 08:01 PM
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Default Re: asic gate count

On May 2, 1:24*am, Thomas Stanka <[email protected]>
wrote:
> On 1 Mai, 21:54, "[email protected]"
>
> <[email protected]> wrote:
> > Ok. I have my design finalized. The fir length would be 64 operating
> > on 32 bit wide word. Now could you please hint me on estimating gate
> > count ?

>
> Is it serial or parallel? Using RAM or FF? Which ASIC technology?
> With tight timing constraints or relaxed timing?
>
> My guess would be 65x32 for storage of input and result and two adders
> size 32 bit.
>
> ASIC gate count is a value gained by guess of numbers multiplied with
> e^n with n being a marketing factor (technical oriented people assume
> n=random(unconstrained) as you can't understand calculation of n if
> you'r not member of a marketing department)
>
> bye Thomas


it will be parallel implementation using RAM and relaxed timing. Any
help is appreciated.

Thanks,
Vijayant
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