Hello everyone,
I have a verilog design that is tested and works properly with
ModelSim simulator. I have synthesized it with Xilinx Project
Navigator tool using XST. I want to verify if the design works
properly(after synthesis) before I can go on with downloading the BIT
stream onto a Xilinx
FPGA board.
I could not find a way to do this. Could anyone please help me in this
matter.
Thanks a lot,
Kumar