FPGA Central

Hi,

I have an entity which has a synchronous reset. Therefore the output is 'X'
until a f_edge(clk) occurs with rst='1'.
What would the value of 'X' be in hardware before the clock edge '0', '1' or
either?????

Thanks.

Matt North wrote:
> Hi,
>
> I have an entity which has a synchronous reset. Therefore the output is 'X'
> until a f_edge(clk) occurs with rst='1'.
> What would the value of 'X' be in hardware before the clock edge '0', '1' or
> either?????

Either a '0' or a '1'.

Paul.

X is dependent on the start up condition of the transistor and can be
0 or 1 or anything inbetween.