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  #1 (permalink)  
Old 10-28-2003, 11:07 AM
Valentin Tihomirov
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Default Will this generate different HW?


The question may a bit silly one but anyway... Assuming the process is
synchronous.

(a)

Ack <= Loading;

(b)

if Loading = '1' then
Ack <= '1';
else
Ack <= '0';
end if;

or the same

Ack <= '0';
if Loading = '1' then
Ack <= '1';
end if;


The first should assign a signal directly while second assigns an output of
a mux.


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  #2 (permalink)  
Old 10-28-2003, 04:28 PM
Mike Treseler
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Default Re: Will this generate different HW?

Valentin Tihomirov wrote:
> The question may a bit silly one but anyway... Assuming the process is
> synchronous.
>
> (a)
>
> Ack <= Loading;
>
> (b)
>
> if Loading = '1' then
> Ack <= '1';
> else
> Ack <= '0';
> end if;
>
> or the same
>
> Ack <= '0';
> if Loading = '1' then
> Ack <= '1';
> end if;
>
>
> The first should assign a signal directly while second assigns an output of
> a mux.


All three examples assign Ack with the value of
Loading from the previous clock edge.

I would expect synthesis to be the same in
all three cases. Try it and see.

For simulation,(b) zero's out H L and Z
while (a) does not.

-- Mike Treseler

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  #3 (permalink)  
Old 10-28-2003, 04:29 PM
Mike
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Default Re: Will this generate different HW?

I would expect the last two statements to be minimized to the equivalent of
the first one.


"Valentin Tihomirov" <[email protected]> wrote in message
news:[email protected]
>
> The question may a bit silly one but anyway... Assuming the process is
> synchronous.
>
> (a)
>
> Ack <= Loading;
>
> (b)
>
> if Loading = '1' then
> Ack <= '1';
> else
> Ack <= '0';
> end if;
>
> or the same
>
> Ack <= '0';
> if Loading = '1' then
> Ack <= '1';
> end if;
>
>
> The first should assign a signal directly while second assigns an output

of
> a mux.
>
>



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  #4 (permalink)  
Old 10-29-2003, 10:25 AM
Lars Wehmeyer
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Default Re: Will this generate different HW?

Mike Treseler wrote:
> All three examples assign Ack with the value of
> Loading from the previous clock edge.
>
> I would expect synthesis to be the same in
> all three cases. Try it and see.
>
> For simulation,(b) zero's out H L and Z
> while (a) does not.


I guess this is the point: what are the data types of your
signals? If it's BIT, then they might be the same.
If they're STD_LOGIC, they behave differently and should
thus generate different hardware.

Lars
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  #5 (permalink)  
Old 10-29-2003, 11:59 AM
Valentin Tihomirov
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Default Re: Will this generate different HW?

What are the considerations to choose between the styles?


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  #6 (permalink)  
Old 10-29-2003, 04:48 PM
Mike Treseler
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Default Re: Will this generate different HW?

Valentin Tihomirov wrote:
> What are the considerations to choose between the styles?


1. Easy to read and understand.
2. Compatible with your tools.

-- Mike Treseler

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  #7 (permalink)  
Old 11-03-2003, 08:52 AM
Thomas Stanka
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Default Re: Will this generate different HW?

Lars Wehmeyer <[email protected]> wrote:
> Mike Treseler wrote:
> > All three examples assign Ack with the value of
> > Loading from the previous clock edge.

[..]
> > For simulation,(b) zero's out H L and Z
> > while (a) does not.

>
> I guess this is the point: what are the data types of your
> signals? If it's BIT, then they might be the same.
> If they're STD_LOGIC, they behave differently and should
> thus generate different hardware.


No. The simulations may differ, but I expect no synthesis tool to
produce different HW. Std_Logic differs from Bit only during
simulations.

bye Thomas
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