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Old 09-10-2003, 04:44 AM
walala
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Default what is wrong with my VHDL code? I am so dissappointed...

Dear all,

I have posted several questions here recently and got a lot very
helpful answers... they are really helpful and I really appreciate
that... thank you all...

However I am still stuck with the same probelm... , which is now my
most headache... I don't know why: pre-synthesis simulation and
post-synthesis simulation show it is correct; but after layout and
netlist extraction, the post-layout simulation show it is wrong... I
really don't know why and I am swamped!

The code is here: in my pre-layout simulation, I give input test
bench:

--x <= (-8, 3, -2, -4, 3, -1);
x <= (B"11111111000", B"00000000011", B"11111111110",
B"11111111100", B"00000000011", B"11111111111"); -- 11 bits input...

The the correct t1=-256, t2=132, t6=-88, t10=-168, t12=186,
t22=-42...

In my post-layout simulation, I use nanosim to supply the same test
vector, the results came to be:

t1=-1x(no waveform for the lower four bits of t1), t2=xxxxx,
t6=xxxxx, t10=-42, t12=93, t22=-168,...

It is really strange that t10, t12, t22 have some relationship with
the expected values...But I really don't know why such a simple
circuit does not work...

I suspected that the Synopsys DC does not synthesize the code
correctly... For example, I am assuming that all my arithmetic
operations are signed, maybe Synopsys does not think all the
operations are signed?

Can anybody give me a hand out of this swamp?

Thank you very much,

-Wallala

-------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_signed.ALL;

PACKAGE MYTYPES IS
SUBTYPE INPUT_WORD IS STD_LOGIC_VECTOR(10 downto 0); -- -1024
TO 1023;
SUBTYPE OUTPUT_BYTE IS STD_LOGIC_VECTOR(7 downto 0); -- -128
TO 127;
SUBTYPE INTERNAL_WORD IS STD_LOGIC_VECTOR(18 downto 0); --
-65536 TO 65535;
TYPE INPUT_WORD_ARRAY IS ARRAY(0 TO 5) OF INPUT_WORD;
TYPE OUTPUT_BYTE_ARRAY IS ARRAY(0 TO 0) OF OUTPUT_BYTE;
TYPE INTERNAL_WORD_ARRAY IS ARRAY(0 TO 0) OF INTERNAL_WORD;
END PACKAGE MYTYPES;


USE work.mytypes.all;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_signed.ALL;


ENTITY mytry IS
PORT(clk : IN std_logic;
rst : IN std_logic;
x : IN INPUT_WORD_ARRAY;
y : OUT OUTPUT_BYTE_ARRAY;
yout : OUT INTERNAL_WORD;
tt1 : OUT INTERNAL_WORD;
tt2 : OUT INTERNAL_WORD;
tt6 : OUT INTERNAL_WORD;
tt10 : OUT INTERNAL_WORD;
tt12 : OUT INTERNAL_WORD;
tt22 : OUT INTERNAL_WORD
);
END mytry;

ARCHITECTURE flex OF mytry IS

SIGNAL t1, t2, t6, t10, t12, t22: INTERNAL_WORD;
SIGNAL temp1, temp2: INTERNAL_WORD;
SIGNAL temp: INTERNAL_WORD_ARRAY;

BEGIN

t1<=B"00100000"*x(0); --32

t2<=B"00101100"*x(1); --44

t6<=B"00101100"*x(2); --44

t10<=B"00101010"*x(3); --42

t12<=B"00111110"*x(4); --62

t22<=B"00101010"*x(5); --42

tt1<=t1;
tt2<=t2;
tt6<=t6;
tt10<=t10;
tt12<=t12;
tt22<=t22;

temp1<=t1+t6+t22;

temp2<=t2+t12;

temp(0)<= temp1+temp2+t10;

yout <= temp(0);

p2: PROCESS(temp)
BEGIN
if temp(0)(7)='1' then
Y(0) <= temp(0)(15 downto 8) + '1';
else
Y(0) <= temp(0)(15 downto 8);
end if;
END PROCESS p2;

END flex;

-------------------------------------------------------

Synopsys DC LOG FILE(Selected. I have ignored them... but I do think I
should have not ignored them... was I right?):

-------------------------------------------------------

Warning: There is a data discrepancy between the db and the output
file. This might cause a problem for back-annotation. Please run
change_names -rule vhdl before writing out the file. (VHDL-286)

....

Warning: Verilog 'assign' or 'tran' statements are written out. (VO-4)

....


Warning: In design 'myidct', a pin on submodule 'mul_48/mult/mult' is
connected to logic 1 or logic 0. (LINT-32)
Pin 'B[6]' is connected to logic 0.
Pin 'B[5]' is connected to logic 1.
Pin 'B[4]' is connected to logic 0.

....

Warning: In design 'myidct_DW02_mult_11_7_4', port 'B[6]' is not
connected to any nets. (LINT-28)

....
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  #2 (permalink)  
Old 09-10-2003, 04:23 PM
Ralf Hildebrandt
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Default Re: what is wrong with my VHDL code? I am so dissappointed...

Hi walala!


> ENTITY mytry IS
> PORT(clk : IN std_logic;
> rst : IN std_logic;
> x : IN INPUT_WORD_ARRAY;
> y : OUT OUTPUT_BYTE_ARRAY;
> yout : OUT INTERNAL_WORD;
> tt1 : OUT INTERNAL_WORD;
> tt2 : OUT INTERNAL_WORD;
> tt6 : OUT INTERNAL_WORD;
> tt10 : OUT INTERNAL_WORD;
> tt12 : OUT INTERNAL_WORD;
> tt22 : OUT INTERNAL_WORD
> );
> END mytry;


Most synthesis tools are configured to write entitys with only
std_(U)logic(_vector). Other types like signed, integer and your
manually defined arrays are ignored (or converted to std_(U)logic(_vector)).

Check your synthesis tool, how it is configured - or (even better):
Don't use any other types than std_(U)logic(_vector).


If your synthesis tool is configured to modify the entity and to not
write back the new entity to the synthesized netlist, you will have
pretty much trouble. (This configuration is common for synthesis tools.)

Ralf

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  #3 (permalink)  
Old 09-10-2003, 05:15 PM
walala
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Default Re: what is wrong with my VHDL code? I am so dissappointed...

Hi, Ralf,

Thank you very much for your answer.

> Check your synthesis tool, how it is configured - or (even better):
> Don't use any other types than std_(U)logic(_vector).


Although I defined some subtype and types, but they are based on
std_logic_vector... is that a problem? By the way, I have passed the
post-synthesis simulation by Modelsim, it is the post-layout simulation that
I failed... should I blame the layout too -- Silicon Ensemble, or the
synthesis tool -- Synopsys DC?

>
> If your synthesis tool is configured to modify the entity and to not
> write back the new entity to the synthesized netlist, you will have
> pretty much trouble. (This configuration is common for synthesis tools.)
>


I am using Synopsys Design Compiler... can you tell me which configuration I
should change?

thanks a lot,

-walala


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  #4 (permalink)  
Old 09-10-2003, 08:47 PM
Ralf Hildebrandt
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Posts: n/a
Default Re: what is wrong with my VHDL code? I am so dissappointed...

Hi walala!


>>Check your synthesis tool, how it is configured - or (even better):
>>Don't use any other types than std_(U)logic(_vector).


> Although I defined some subtype and types, but they are based on
> std_logic_vector... is that a problem?


It may be. Often synthesis tools are configured to build entitys only
with std_(U)logic(_vector), but this is only a common configuration.

But it would be a good way to use everytime std_(U)logic(_vector). At
least at the top-level there is no other option - AFAIK.


> By the way, I have passed the
> post-synthesis simulation by Modelsim, it is the post-layout simulation that
> I failed...


Well ... then the "entity-problem" did not occur.

What about a timing problem? Are you running your post-layout simulation
too fast?


> should I blame the layout too -- Silicon Ensemble, or the
> synthesis tool -- Synopsys DC?


I would guess that it is an error within the layout, not within
synthesis. And last of all: Everytime I was searching for a bug, the
reason I found was my mistake - no error within any tool.



>>If your synthesis tool is configured to modify the entity and to not
>>write back the new entity to the synthesized netlist, you will have
>>pretty much trouble. (This configuration is common for synthesis tools.)


> I am using Synopsys Design Compiler... can you tell me which configuration I
> should change?


The configuration file is .synopsys_dc_setup
But I can't tell you whitch option is responsible for this. My
..synopsys_dc_setup was pre-configured this way and I simply accepted it. ;-)

Ralf

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