FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > VHDL

VHDL comp.lang.vhdl newsgroup / Usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 10-02-2003, 03:54 AM
walala
Guest
 
Posts: n/a
Default what do you guys do if Synopsys DC says it runs out of memory?

Dear all,

This might be more towards synthesis...

I keep getting "run out of memory" error message from my Synopsys Design
Compiler... The strangest thing is that the same design, sometimes can pass,
sometimes will fail "running out of memory"... Sometimes the "memory value"
is 4GB, sometimes it is 1GB...

Here is my script file and here is my error message... What do you guys do
when you meet with such problem? Could you share with some of your
experiences?

Thanks a lot

-Walala

---------------------------------------------------------
Script:

$SYNOPSYS/sparcOS5/syn/bin/dc_shell-t <<!
redirect myidct_zero1cmu.log {
analyze -format vhdl -lib WORK {myidct_zero1cmu.vhd}
elaborate myidct_zero1cmu -arch "flex" -lib WORK -update
ungroup -all -flatten
create_clock "CLK" -name "CLK" -period 60
compile -map_effort medium -area_effort high
current_design .
report_timing -path full -delay max -max_paths 1 -nworst 1 >
reports/\$current_design.rep
report_area >> reports/\$current_design.rep
report_resources -hierarchy >> reports/\$current_design.rep
write -format vhdl -hierarchy -output "mapped/\$current_design.vhd"
write -format verilog -hierarchy -output "mapped/\$current_design.v"
echo "\nScript Done\n"
echo "\nChecking Design\n"
check_design
}
!

-------------------------------------------------------------

Error message:

90 > ./scripts/myidct_zero1cmu.scr

Behavioral Compiler (TM)
DC Professional (TM)
DC Expert (TM)
DC Ultra (TM)
VHDL Compiler (TM)
HDL Compiler (TM)
Library Compiler (TM)
Power Compiler (TM)
DFT Compiler (TM)
BSD Compiler
DesignWare Developer (TM)
DesignPower (TM)

Version 2001.08-SP2 for sparcOS5 -- Feb 05, 2002
Copyright (c) 1988-2001 by Synopsys, Inc.
ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys, Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Initializing...
dc_shell-t>

Out of memory.
(Memory allocated = 4103759 K bytes)



Reply With Quote
  #2 (permalink)  
Old 10-02-2003, 09:47 AM
Tuukka Toivonen
Guest
 
Posts: n/a
Default Re: what do you guys do if Synopsys DC says it runs out of memory?

In article <[email protected]>, walala wrote:
> I keep getting "run out of memory" error message from my Synopsys Design


- Check if there are some memory limits that could be changed. In bash,
ulimit -a
ulimit -S -d 8000000
In tcsh, the command is different (man tcsh, search for "limit").
- Can you increase swap size?
- Can you synthesize your design in small parts?
- Can you change/lower synthesizer optimization level?
- Are you using some structures in VHDL that take lots of space
(e.g. generate for ...)? Could they be written differently?

> ungroup -all -flatten


- Would it help not to use "flatten"?

> compile -map_effort medium -area_effort high


- Would it help to use low effort?
Reply With Quote
  #3 (permalink)  
Old 10-02-2003, 07:23 PM
Richard Iachetta
Guest
 
Posts: n/a
Default Re: what do you guys do if Synopsys DC says it runs out of memory?

In article <[email protected]>, [email protected] says...
> Dear all,
>
> This might be more towards synthesis...
>
> I keep getting "run out of memory" error message from my Synopsys Design
> Compiler... The strangest thing is that the same design, sometimes can pass,
> sometimes will fail "running out of memory"... Sometimes the "memory value"
> is 4GB, sometimes it is 1GB...
>
> Here is my script file and here is my error message... What do you guys do
> when you meet with such problem? Could you share with some of your
> experiences?
>
> Thanks a lot
>
> -Walala


Walala, you should probably Synopsys rather than comp.lang.vhdl. Just email
[email protected]. You may need to switch to the 64-bit version of DC.

--
Rich Iachetta
I do not speak for IBM
Reply With Quote
  #4 (permalink)  
Old 10-03-2003, 11:41 AM
Renaud Pacalet
Guest
 
Posts: n/a
Default Re: what do you guys do if Synopsys DC says it runs out of memory?

walala a écrit :
> Dear all,
>
> This might be more towards synthesis...
>
> I keep getting "run out of memory" error message from my Synopsys Design
> Compiler... The strangest thing is that the same design, sometimes can pass,
> sometimes will fail "running out of memory"... Sometimes the "memory value"
> is 4GB, sometimes it is 1GB...
>
> Here is my script file and here is my error message... What do you guys do
> when you meet with such problem?


Modify your design. You're trying to synthesize flat a brute force
boolean description of an 8x8 IDCT. Most synthesizers will run out of
memory. If one doesn't then it will, once you'll add the IQUANT module
and expect some logic optimization between the two modules ;-) IDCT is a
quite regular algorithm, it's very easy to describe in a way that most
optimizers will optimize very fast without any memory problem. Try a
distributed arithmetic architecture. I worked for years on MPEG
implementations, rewieved dozens of papers about "the best IDCT
implementation in the world" and still believe distributed arithmetic is
preferable, whatever your cost function is.

Best regards,
--
Renaud Pacalet, GET/ENST/COMELEC/LabSoC
Institut Eurecom BP 193, 2229 route des Cretes
F-06904 Sophia-Antipolis Cedex
Tel : +33 (0) 4 9300 2770
Fax : +33 (0) 4 9300 2627
Fight Spam! Join EuroCAUCE: http://www.euro.cauce.org/

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
HI guys...about EDK [email protected] FPGA 0 02-06-2007 01:51 AM
To Xilinx guys out there - microblaze mapping problem [email protected] FPGA 6 11-07-2006 03:30 PM
Hello Guys, Please let me know if you need any Cisco [email protected] FPGA 0 08-17-2006 09:27 PM
salary ballpark please guys Dave FPGA 27 04-19-2005 11:32 AM
Am I right in my VHDL code? Synopsys DC runs for ever... walala VHDL 8 09-24-2003 03:04 PM


All times are GMT +1. The time now is 02:36 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved