FPGA Central

Dear all,

This might be more towards synthesis...

I keep getting "run out of memory" error message from my Synopsys Design
Compiler... The strangest thing is that the same design, sometimes can pass,
sometimes will fail "running out of memory"... Sometimes the "memory value"
is 4GB, sometimes it is 1GB...

Here is my script file and here is my error message... What do you guys do
when you meet with such problem? Could you share with some of your
experiences?

Thanks a lot

-Walala

---------------------------------------------------------
Script:

$SYNOPSYS/sparcOS5/syn/bin/dc_shell-t <<!
redirect myidct_zero1cmu.log {
analyze -format vhdl -lib WORK {myidct_zero1cmu.vhd}
elaborate myidct_zero1cmu -arch "flex" -lib WORK -update
ungroup -all -flatten
create_clock "CLK" -name "CLK" -period 60
compile -map_effort medium -area_effort high
current_design .
report_timing -path full -delay max -max_paths 1 -nworst 1 >
reports/\$current_design.rep
report_area >> reports/\$current_design.rep
report_resources -hierarchy >> reports/\$current_design.rep
write -format vhdl -hierarchy -output "mapped/\$current_design.vhd"
write -format verilog -hierarchy -output "mapped/\$current_design.v"
echo "\nScript Done\n"
echo "\nChecking Design\n"
check_design
}
!

-------------------------------------------------------------

Error message:

90 > ./scripts/myidct_zero1cmu.scr

Behavioral Compiler (TM)
DC Professional (TM)
DC Expert (TM)
DC Ultra (TM)
VHDL Compiler (TM)
HDL Compiler (TM)
Library Compiler (TM)
Power Compiler (TM)
DFT Compiler (TM)
BSD Compiler
DesignWare Developer (TM)
DesignPower (TM)

Version 2001.08-SP2 for sparcOS5 -- Feb 05, 2002
Copyright (c) 1988-2001 by Synopsys, Inc.
ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys, Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Initializing...
dc_shell-t>

Out of memory.
(Memory allocated = 4103759 K bytes)

In article <[email protected]>, walala wrote:
> I keep getting "run out of memory" error message from my Synopsys Design

- Check if there are some memory limits that could be changed. In bash,
ulimit -a
ulimit -S -d 8000000
In tcsh, the command is different (man tcsh, search for "limit").
- Can you increase swap size?
- Can you synthesize your design in small parts?
- Can you change/lower synthesizer optimization level?
- Are you using some structures in VHDL that take lots of space
(e.g. generate for ...)? Could they be written differently?

> ungroup -all -flatten

- Would it help not to use "flatten"?

> compile -map_effort medium -area_effort high

- Would it help to use low effort?

In article <[email protected]>, [email protected] says...
> Dear all,
>
> This might be more towards synthesis...
>
> I keep getting "run out of memory" error message from my Synopsys Design
> Compiler... The strangest thing is that the same design, sometimes can pass,
> sometimes will fail "running out of memory"... Sometimes the "memory value"
> is 4GB, sometimes it is 1GB...
>
> Here is my script file and here is my error message... What do you guys do
> when you meet with such problem? Could you share with some of your
> experiences?
>
> Thanks a lot
>
> -Walala

Walala, you should probably Synopsys rather than comp.lang.vhdl. Just email
[email protected]com. You may need to switch to the 64-bit version of DC.

--
Rich Iachetta
I do not speak for IBM

walala a écrit :
> Dear all,
>
> This might be more towards synthesis...
>
> I keep getting "run out of memory" error message from my Synopsys Design
> Compiler... The strangest thing is that the same design, sometimes can pass,
> sometimes will fail "running out of memory"... Sometimes the "memory value"
> is 4GB, sometimes it is 1GB...
>
> Here is my script file and here is my error message... What do you guys do
> when you meet with such problem?

Modify your design. You're trying to synthesize flat a brute force
boolean description of an 8x8 IDCT. Most synthesizers will run out of
memory. If one doesn't then it will, once you'll add the IQUANT module
and expect some logic optimization between the two modules ;-) IDCT is a
quite regular algorithm, it's very easy to describe in a way that most
optimizers will optimize very fast without any memory problem. Try a
distributed arithmetic architecture. I worked for years on MPEG
implementations, rewieved dozens of papers about "the best IDCT
implementation in the world" and still believe distributed arithmetic is
preferable, whatever your cost function is.

Best regards,
--
Renaud Pacalet, GET/ENST/COMELEC/LabSoC
Institut Eurecom BP 193, 2229 route des Cretes
F-06904 Sophia-Antipolis Cedex
Tel : +33 (0) 4 9300 2770
Fax : +33 (0) 4 9300 2627
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