Ahmed Samieh schrieb:
> but, i the question still, what is the reason of this global clock
> buffer ....
> while another 2 processes like :
>
> p1 : process(clk,...)
> begin
> if rising_edge(clk) then
> ....
> end if;
> end process p1;
> p2 : process(clk,...)
> begin
> if falling_edge(clk) then
> ....
> end if;
> end process p1;
>
> will not resulte the warning of global clock buffer !!
>
> is there any explanation ?
A global clock buffer is a special strong driver for a clock. The clock
is routed via special clock wires. It is not fed into the normal logic
wires of the
FPGA. This reduces clock skew to a minimum.
You can't just make a hook to this global clock wire and use this global
wherever you want. The global clock is routed to the clk-Input of any
Flipflop (better: to a multiplexer in front of this clk-Input).
Therefore you can use the global clock with every flipflop (rising_edge
/ falling_edge). But it is often (depending on the
FPGA) impossible to
use this global clock as an input to combinational logic.
If you use the clock inside combinational logic, the clock can't be
routed via the global net and has to be routed via a normal logic net.
Because this results in a lot of skew the routing tool will output a
warning.
Ralf