FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > VHDL

VHDL comp.lang.vhdl newsgroup / Usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 09-27-2003, 11:38 AM
Niv
Guest
 
Posts: n/a
Default Virtex2 & ISE4.2

Help!
Doing a design in Virtex2 (XC2V250 so uite small).
The VHDL synthesises OK to an .edf file, plus another .edf for an IP core.

When I run PAR it fails the first hyurdle saying it can't find some blocks,
but why are they missing?

Message is "ngdbuild error 604"

Is it that 4.2 is old and can't fully handle Virtex2?

TIA, Niv.


Reply With Quote
  #2 (permalink)  
Old 09-29-2003, 04:54 PM
Mike Treseler
Guest
 
Posts: n/a
Default Re: Virtex2 & ISE4.2

Niv wrote:
> Help!
> Doing a design in Virtex2 (XC2V250 so uite small).
> The VHDL synthesises OK to an .edf file, plus another .edf for an IP core.
>
> When I run PAR it fails the first hyurdle saying it can't find some blocks,
> but why are they missing?


Your vhdl source should include an unbound component
and instance matching the ip name so that the
..edf files can be wired up correctly.

-- Mike Treseler

Reply With Quote
  #3 (permalink)  
Old 09-29-2003, 06:21 PM
Niv
Guest
 
Posts: n/a
Default Re: Virtex2 & ISE4.2

Yes, I realise all that, BUT, the some of the 5 error reports are pointing
to a section of the design that is all VHDL,
and nothing to do with the IP block. The other error messages refer to the
IP block, but I have put the IP .edf in the same
directory as the synthesised .edf for the whole chip.

So, I'm still confused.

PS. I've successfully done all this before with Virtex, on a different
design, with Xilinx "coregen" parts effectively as IP.
all this went just fine, but now with Virtex 2 I'm very stuck.

Niv.

"Mike Treseler" <[email protected]> wrote in message
news:[email protected]
> Niv wrote:
> > Help!
> > Doing a design in Virtex2 (XC2V250 so uite small).
> > The VHDL synthesises OK to an .edf file, plus another .edf for an IP

core.
> >
> > When I run PAR it fails the first hyurdle saying it can't find some

blocks,
> > but why are they missing?

>
> Your vhdl source should include an unbound component
> and instance matching the ip name so that the
> .edf files can be wired up correctly.
>
> -- Mike Treseler
>



Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
ddr in virtex2 raphael FPGA 1 04-06-2006 05:14 PM
Conflicts between ISE4.2 and win2000 SP4 [email protected] FPGA 6 01-13-2006 04:19 PM
Compiling library problem in Xilinx ISE4.0? Lee FPGA 3 04-23-2004 02:28 AM


All times are GMT +1. The time now is 05:04 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved