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  #1 (permalink)  
Old 10-12-2003, 09:55 AM
Yttrium
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Posts: n/a
Default [VHDL] a testbench question (bringing out states) - noob

Hey, i can write some small VHDL source codes but from now on i want to
write some real interesting stuff (for a project) and i was wondering how
you bring out states from your VHDL module to your testbench when they are
defined as follow:

type DDR_STATE_TYPE is ( IDLE, PRECHRG_ST, AUTO_RFSH_ST, SELF_RFSH_ST,
LOAD_MR_ST,
BURST_TERM_ST, ACTIVE_ST, WAIT_READ_ST, WAIT_READ_ST2, READ_ST,
CAS_DELAY_ST, READ_DATA_ST, RD_DONE_ST, WAIT_WRITE_ST, WRITE_ST,
WRITE_DATA_ST, WAIT_TWR, WAIT_TRP );

signal ddr_prs_state, ddr_nxt_state : DDR_STATE_TYPE;

for now i brought them out with the select statement but that's to much work
if you have about 3 SM in a VHDL module so i was wondering if there wasn't a
easier way some of you bring them out to the testbenc...

it might be a 'stupid' question but anyway ...

thanx in advance,

Yttrium


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  #2 (permalink)  
Old 10-12-2003, 08:17 PM
MM
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Posts: n/a
Default Re: [VHDL] a testbench question (bringing out states) - noob

Yttrium,

You could make an output from your module of the DDR_STATE_TYPE and define
this type globally, so that both the module and the test bench know what it
is. On the other hand any decent VHDL simulator will allow you to see any
signal in any module without bringing it out.

/Mikhail



"Yttrium" <[email protected]> wrote in message
news:[email protected]
> Hey, i can write some small VHDL source codes but from now on i want to
> write some real interesting stuff (for a project) and i was wondering how
> you bring out states from your VHDL module to your testbench when they are
> defined as follow:
>
> type DDR_STATE_TYPE is ( IDLE, PRECHRG_ST, AUTO_RFSH_ST, SELF_RFSH_ST,
> LOAD_MR_ST,
> BURST_TERM_ST, ACTIVE_ST, WAIT_READ_ST, WAIT_READ_ST2, READ_ST,
> CAS_DELAY_ST, READ_DATA_ST, RD_DONE_ST, WAIT_WRITE_ST, WRITE_ST,
> WRITE_DATA_ST, WAIT_TWR, WAIT_TRP );
>
> signal ddr_prs_state, ddr_nxt_state : DDR_STATE_TYPE;
>
> for now i brought them out with the select statement but that's to much

work
> if you have about 3 SM in a VHDL module so i was wondering if there wasn't

a
> easier way some of you bring them out to the testbenc...
>
> it might be a 'stupid' question but anyway ...
>
> thanx in advance,
>
> Yttrium
>
>



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  #3 (permalink)  
Old 10-14-2003, 07:51 PM
Yttrium
Guest
 
Posts: n/a
Default Re: [VHDL] a testbench question (bringing out states) - noob

well, i've been using ModelSim (together with WebPack from Xilinx) and there
you'll always have to bring them out ...

so what software are you talking about?


"MM" <[email protected]> wrote in message
news:[email protected]
> Yttrium,
>
> You could make an output from your module of the DDR_STATE_TYPE and define
> this type globally, so that both the module and the test bench know what

it
> is. On the other hand any decent VHDL simulator will allow you to see any
> signal in any module without bringing it out.
>
> /Mikhail
>
>
>
> "Yttrium" <[email protected]> wrote in message
> news:[email protected]
> > Hey, i can write some small VHDL source codes but from now on i want to
> > write some real interesting stuff (for a project) and i was wondering

how
> > you bring out states from your VHDL module to your testbench when they

are
> > defined as follow:
> >
> > type DDR_STATE_TYPE is ( IDLE, PRECHRG_ST, AUTO_RFSH_ST, SELF_RFSH_ST,
> > LOAD_MR_ST,
> > BURST_TERM_ST, ACTIVE_ST, WAIT_READ_ST, WAIT_READ_ST2, READ_ST,
> > CAS_DELAY_ST, READ_DATA_ST, RD_DONE_ST, WAIT_WRITE_ST, WRITE_ST,
> > WRITE_DATA_ST, WAIT_TWR, WAIT_TRP );
> >
> > signal ddr_prs_state, ddr_nxt_state : DDR_STATE_TYPE;
> >
> > for now i brought them out with the select statement but that's to much

> work
> > if you have about 3 SM in a VHDL module so i was wondering if there

wasn't
> a
> > easier way some of you bring them out to the testbenc...
> >
> > it might be a 'stupid' question but anyway ...
> >
> > thanx in advance,
> >
> > Yttrium
> >
> >

>
>



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  #4 (permalink)  
Old 10-14-2003, 08:30 PM
MM
Guest
 
Posts: n/a
Default Re: [VHDL] a testbench question (bringing out states) - noob

"Yttrium" <[email protected]> wrote in message
news:KAXib.77[email protected]
> well, i've been using ModelSim (together with WebPack from Xilinx) and

there
> you'll always have to bring them out ...
>
> so what software are you talking about?


I am using Aldec Active-HDL, but I can hardly believe what you are saying
about ModelSim... Perhaps we are talking about different things. What I
mean, is that you can bring any internal signal to your waveform window. Of
course, if you want to do anything with this signal in the test bench it has
to be in its scope.

/Mikhail


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  #5 (permalink)  
Old 10-14-2003, 09:09 PM
Mike Treseler
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Posts: n/a
Default Re: [VHDL] a testbench question (bringing out states) - noob

MM wrote:

> I am using Aldec Active-HDL, but I can hardly believe what you are saying
> about ModelSim... Perhaps we are talking about different things. What I
> mean, is that you can bring any internal signal to your waveform window. Of
> course, if you want to do anything with this signal in the test bench it has
> to be in its scope.


That is correct.
The testbench can only see the port signals of
it's own dut instances.
You can either infer proper state transitions by watching
the port outputs, or you can add test ports that are
unused for synthesis.

-- Mike Treseler

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  #6 (permalink)  
Old 10-14-2003, 09:10 PM
Jim Lewis
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Posts: n/a
Default Re: [VHDL] a testbench question (bringing out states) - noob

In modelsim if you want to sneak the value of
a signal out of the design, take a look at the
signal spy package. Granted right now this is not
a standard, but something like this is planned
for the next language revision.

You will probably either need to define your
enumerated type in a package
(so it will also be visible to the testbench) or
convert your enumerated type to std_logic_vector
using a case statement in your design.

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~

Yttrium wrote:

> Hey, i can write some small VHDL source codes but from now on i want to
> write some real interesting stuff (for a project) and i was wondering how
> you bring out states from your VHDL module to your testbench when they are
> defined as follow:
>
> type DDR_STATE_TYPE is ( IDLE, PRECHRG_ST, AUTO_RFSH_ST, SELF_RFSH_ST,
> LOAD_MR_ST,
> BURST_TERM_ST, ACTIVE_ST, WAIT_READ_ST, WAIT_READ_ST2, READ_ST,
> CAS_DELAY_ST, READ_DATA_ST, RD_DONE_ST, WAIT_WRITE_ST, WRITE_ST,
> WRITE_DATA_ST, WAIT_TWR, WAIT_TRP );
>
> signal ddr_prs_state, ddr_nxt_state : DDR_STATE_TYPE;
>
> for now i brought them out with the select statement but that's to much work
> if you have about 3 SM in a VHDL module so i was wondering if there wasn't a
> easier way some of you bring them out to the testbenc...
>
> it might be a 'stupid' question but anyway ...
>
> thanx in advance,
>
> Yttrium
>
>


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  #7 (permalink)  
Old 10-15-2003, 06:00 AM
Srinivasan Venkataramanan
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Posts: n/a
Default Re: [VHDL] a testbench question (bringing out states) - noob

Hi,
As Jim Lewis mentioned, many simulators today support a PLI - enabled
feature to let users probe internal signal in VHDL. Modelsim names it as
Signalspy, Cadence - NC_MIRROR, Aldec - Signal Agent.

Some time back I created a common package which will behave equally well
across all these 3 simulators, if there is enough interest I will upload it
to my web page.

Regards,
Srinivasan

"MM" <[email protected]> wrote in message
news:[email protected]
> "Yttrium" <[email protected]> wrote in message
> news:[email protected]
> > well, i've been using ModelSim (together with WebPack from Xilinx) and

> there
> > you'll always have to bring them out ...
> >
> > so what software are you talking about?

>
> I am using Aldec Active-HDL, but I can hardly believe what you are saying
> about ModelSim... Perhaps we are talking about different things. What I
> mean, is that you can bring any internal signal to your waveform window.

Of
> course, if you want to do anything with this signal in the test bench it

has
> to be in its scope.
>
> /Mikhail
>
>


--
Srinivasan Venkataramanan
Senior Verification Engineer
Software & Silicon Systems India Pvt Ltd. - an Intel company
Bangalore, India

http://www.noveldv.com http://www.deeps.org

I don't speak for Intel


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  #8 (permalink)  
Old 10-15-2003, 07:03 PM
Yttrium
Guest
 
Posts: n/a
Default Re: [VHDL] a testbench question (bringing out states) - noob


"Srinivasan Venkataramanan" <[email protected]_spam.co.in> wrote
in message news:[email protected]
> Hi,
> As Jim Lewis mentioned, many simulators today support a PLI - enabled
> feature to let users probe internal signal in VHDL. Modelsim names it as
> Signalspy, Cadence - NC_MIRROR, Aldec - Signal Agent.


yep, i followed the advice of jim lewis and indeed found this link
http://www.model.com/demo/tours/sign...ewlet_swf.html
at the modelsim site and am now trying it out!!!! thanx for the tip!!! this
is really interesting

> Some time back I created a common package which will behave equally well
> across all these 3 simulators, if there is enough interest I will upload

it
> to my web page.


i would be interested ;-) ... thanx in advance!

> Regards,
> Srinivasan
>
> "MM" <[email protected]> wrote in message
> news:[email protected]
> > "Yttrium" <[email protected]> wrote in message
> > news:[email protected]
> > > well, i've been using ModelSim (together with WebPack from Xilinx) and

> > there
> > > you'll always have to bring them out ...
> > >
> > > so what software are you talking about?

> >
> > I am using Aldec Active-HDL, but I can hardly believe what you are

saying
> > about ModelSim... Perhaps we are talking about different things. What I
> > mean, is that you can bring any internal signal to your waveform window.

> Of
> > course, if you want to do anything with this signal in the test bench it

> has
> > to be in its scope.
> >
> > /Mikhail
> >
> >

>
> --
> Srinivasan Venkataramanan
> Senior Verification Engineer
> Software & Silicon Systems India Pvt Ltd. - an Intel company
> Bangalore, India
>
> http://www.noveldv.com http://www.deeps.org
>
> I don't speak for Intel
>
>



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