Ali,
See the package IEEE.Fixed_Pkg:
http://www.eda.org/vhdl-200x/vhdl-20...ges/files.html
Since it is not yet standardized, you will temporarily need to
compile it into your own library to use it.
Cheers,
Jim
P.S.
Also note Ralf's post about using multiplication instead of division.
--
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Jim Lewis
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SynthWorks Design Inc.
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> Hello All,
>
> How can I perform division for the below mentioned :
>
> Data_In : std_logic_vector(33 downto 0);
> constant ZETA :std_logic_vector(8 downto 0) := "100100001";
>
> Now : Result <= Data_in / Zeta;
>
> I intend to represent the result rounded to (16,-7) (i.e., 9 bits
> integer and 7 bits fractional)
>
> NOTE: The Constant(ZETA) which I have mentioned is Canonical Signed
> Digit Representation of An Integer value = -0.8710935
>
>
> Kindly suggest me a solution to this problem !
>
> Regards,
> Ali