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-   -   VHDL language question regarding placement of attributes (http://www.fpgacentral.com/group/showthread.php?t=69546)

KJ 09-21-2006 05:45 PM

VHDL language question regarding placement of attributes
 
Can someone point me to the appropriate verbage in the LRM that
supports or refutes the following statement copied from Synplify's help
manual. I have code of the type that Synplify lists that compiles with
Modelsim and Quartus without complaint but Synplify gives the warning
so I'd like to know, per the LRM, who is correct? Synplify or
Modelsim?

The Synplify online help goes on to explain how they believe the
attribute declaration belongs inside the entity but I'd like to know
which tool is not correctly interpreting the standard before
complaining.

Thanks.
KJ

-- Snippet of online help from Synplify 8.5.1
@W: No such identifier, <q2>, of proper type in current declarative
region
VHDL Compiler Warning CD134
Description:

This warning occurs when the compiler finds a signal that is used in an
attribute, but not declared within the corresponding declarative
region, such as between the architecture definition line and the begin.
In the test case below, qrs is not defined within the declarative
region.

entity dff1 is
port (data, clk, reset, set: in std_logic;
qrs1,qrs2: out std_logic );
end dff1;

architecture async_set_reset of dff1 is
attribute syn_preserve : boolean;
attribute syn_preserve of qrs2 : signal is true;


KJ 09-21-2006 06:50 PM

Re: VHDL language question regarding placement of attributes
 
I did run across some more info (link below) that would seem to
indicate that prior to VHDL-2002 entities and their corresponding
architectures form a single declarative region.

http://www.vhdl.org/isac/IRs-VHDL-2002/IR2042.txt

Per Synplify's online help...

The language information is taken from the most recent VHDL Language
Reference Manual (Revision ANSI/IEEE Std 1076-1993)

This would seem to indicate two things:
- My beef is with Synplify for the error that I'm getting and that
Synplify does not conform to the 1076-1993 standard in this
regard...although perhaps it is conforming to the 2002 standard.
- Somebody needs to send Synplify a copy of the 2002 and 2006 manuals
if they think that 1076-1993 is the 'most recent'. ;)

Also, the link above seemed to indicate that future revisions of the
standard would probably try to fix what they broke by doing this.
Since the 2006 standard has just come out maybe it does.

If anyone who can interpret the LRM better than I can comment I would
still appreciate hearing about it.

Thanks.

KJ


Brian Drummond 09-22-2006 11:07 PM

Re: VHDL language question regarding placement of attributes
 
On 21 Sep 2006 08:45:04 -0700, "KJ" <[email protected]> wrote:

>The Synplify online help goes on to explain how they believe the
>attribute declaration belongs inside the entity but I'd like to know
>which tool is not correctly interpreting the standard before
>complaining.


That has never been my (probably faulty) understanding, but...

>architecture async_set_reset of dff1 is
>attribute syn_preserve : boolean;
>attribute syn_preserve of qrs2 : signal is true;


attribute syn_preserve of qrs2 : label is true;

you can apply attributes to labels in the declarative region; then they
attach to whatever the labels bind to...

it certainly works for component instances which are not named until the
actual instantiation.

- Brian


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