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Old 04-14-2005, 03:56 AM
Jim Lewis
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Default Re: VHDL language of choice?

Ralf Hildebrandt wrote:

> Tim Hubberstey wrote:
>
>
>> Foremost among these, IMO, is the issue of a built-in pre-processor.
>> Nearly every person I have encountered who is just learning VHDL, but
>> has experience with another language, asks: Why is there no
>> pre-processor/macro capability?
>>
>> From the very beginning (VHDL'87), it has been stated that the
>> designers don't want a pre-processor ...

>
>
> Do we need a preprocessor, if something like the generate statements
> would be extended to the signal declaration and to the entity? Such a
> solution would offer configuration using one idea - not two like the
> parameter and defines in Verilog.
>
>
> Ralf


On a similar note, is there another answer for paramterizing
entity interfaces such as introducing some type of interface
abstraction.

---

BTW, the way I currently handle entities is to define all of
the signals. For designs that don't need some of the IO, I
tie off the inputs to constants and leave outputs open.
For FPGA tools this seems to be enough.

For ASIC tools, I instantiate the block inside of another block
with the only the IO I need and then during synthesis, remove
the level of hierarchy for the re-usable component. The result
is a single component without any unused IO. A few more tool
steps but it gets the job done.

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
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  #27 (permalink)  
Old 04-14-2005, 04:10 AM
Jim Lewis
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Default Re: VHDL language of choice?

Tim,
> Possibly not for pre-processing, as long as the pragma issue is
> addressed somehow.

Very few of the synthesis tool pragmas made it into 1076.6
(the VHDL RTL Synthesis Standard). Instead 1076.6 mostly
uses attributes.

Unfortunately, there is nothing a standards organization can
do to prevent tool vendors from doing their own things that
are outside of the language. So I think WRT pragmas, we are
stuck. Perhaps what you need is a switch or configuration for
your synthesis tool that says don't do pragmas or only do IEEE
standard pragmas. With this said, you would have to convince
your tool vendor that it is worthy for them to spend the money
to implement this feature.

If you want more standard attributes in standard IEEE 1076.6,
talk to your tool vendors and tell them the importantance
of standards and ask them to join the 1076.6 working group
(and get them to kick off the next revision of the standard).



> However, I would still like to see a macro capability. Generates are
> powerful and can do many things, but sometimes they either just aren't
> enough (lack of an "else" clause is a big failing), or are way too complex.


We considered this for VHDL-200X fast track, but decided
it is more complex than we wanted to tackle in that revision.
The problem is that every branch through a if/else
generate or case generate would need to create an
independently named block (that can be referenced in
a configuration). Going further should each branch also
have a separate declarative region? There is no reason
that this cannot be worked on in the next phase of
VHDL-200X. The only thing we need is for someone to step
forward who wants to work on it.

I have a number of things I personally want to spend time
on in the next revision. This one unfortunately does not
make my list. Not because it is not worthy - but instead
because there are other things that have higher value to me
(and I am selfish).

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
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