FPGA Central

Hosted by opencores.org:
http://www.opencores.org/projects.cg...lator/overview

Hope people find this useful, I sure do... I placed some sample text
files ('programs') that can be played with. The project can be run in
Modelsim without any changes to get a feel for what its doing. Of
course without a top level FPGA design hooked up to it there won't be
much to see.

This project emulates a CPU for an FPGA under simulation with the use
of text files. It can be used to test an FPGA - CPU interface using
realistic real-world stimuli. One main text file per CPU emulation
instance is used for global CPU commands, and thread spawning. Each
spawned thread is tied to an additional text file to use as its 'source
code'.

Features:
Configuration of clock, and reset, and read latency.
Wait for time period
Wait for signal value (good for interrupts)
Declare local and global variables (bit, vector8, or string)
Nested while loops with separate variable space in each nesting
Nested if conditionals (no new variable space)
Unlimited number of threads
Print variables to a file (line by line)
Write a value or variable to an address
Read a value from an address and place in variable
Read using a DMA and writing values to a file

Thread control:
Each thread runs until it hits a wait or the end of the file. If no
wait is hit, then it will continue to run and choke the system. There
is no DMA write provided as the software supports only 0 latency writes
such that consecutive writes in a while loop perform the DMA. See
ctc.txt lines 24 - 36 for an example of this. All commands other than
wait, read and write take 0 time. Only wait or wait_interruptX cause
the thread switching.