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Old 10-09-2003, 05:40 PM
Eqbal Z
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Default vhdl for data forwarding in a pipeline machine

Hi,

I am very new to vhdl and I am trying to modify this pipeline (5
stage) architecture to include data forwarding. Here is the code that
I use. For some reason it causes the decode to stall forever after a
few instructions. IRTemp is instruction that goes into execute, IRx
goes into memory and IRm goes into write back and IRin is the one that
comes into the decode segment (for which I have included a part). I
have added a 4 signal mux to the architecture.
If anyone can help me with this I would appreciate it.

Thanks
-----------------code segment start----------------
process (IRtemp,adin,bdin,IRin,IRx,IRm,xstall,write_flag,f invalid,bren)
constant REGOUT : std_logic_vector(1 downto 0) := "00";
constant ALUOUT : std_logic_vector(1 downto 0) := "01";
constant RESULT : std_logic_vector(1 downto 0) := "10";
constant DOUT : std_logic_vector(1 downto 0) := "11";
begin
if finvalid = '0' then -- fetch out is valid
dstalltemp <= xstall; -- set dstall to xstall (assume we will
stall if x is stalled)
-- delayed branching segement
if (IRin(15 downto 14) = "00" and IRin(11) = '0') then
invalid <= bren; -- delete instruction after branch from pipe if
not a delayed branch
end if;
-- data forwarding segment
if (IRin(15 downto 14) = "01" or IRin(15 downto 14) = "10") then
-- if this = ALU or MEM

if ((IRtemp(13 downto 11) = IRin(10 downto 8)) and --
EXECUTE DEST
((IRtemp(15 downto 14) = "01" and IRtemp(5) = '0') or --
and memory read
(IRtemp(15 downto 14) = "10") or --
or ALU
(IRtemp(15 downto 14) = "11"))) then --
or set
muxASel <= RESULT; --
adin <= result; ??? when to chose result and when aluout?

elsif ((IRx(13 downto 11) = IRin(10 downto 8)) and --
MEMORY DEST
((IRx(15 downto 14) = "01" and IRx(5) = '0') or --
memory read
(IRx(15 downto 14) = "10") or --
or ALU
(IRx(15 downto 14) = "11"))) then --
or set
muxASel <= DOUT; --
adin <= dout; ???

elsif ((IRm(13 downto 11) = IRin(10 downto 8)) and --
WRITE DEST
((IRm(15 downto 14) = "01" and IRm(5) = '0') or --
memory read
(IRm(15 downto 14) = "10") or --
or ALU
(IRm(15 downto 14) = "11"))) then --
or set
muxASel <= REGOUT;
else
dstalltemp <= xstall;
end if;

if (IRin(3) = '1') then --and -- check second register for
hazards

if ((IRtemp(13 downto 11) = IRin(2 downto 0)) and
-- EXECUTE DEST
((IRtemp(15 downto 14) = "01" and IRtemp(5) = '0') or
-- memory read
(IRtemp(15 downto 14) = "10") or
-- or ALU
(IRtemp(15 downto 14) = "11"))) then
-- or set
muxBSel <= RESULT;
elsif ((IRx(13 downto 11) = IRin(2 downto 0)) and
-- MEMORY DEST
((IRx(15 downto 14) = "01" and IRx(5) = '0') or
-- memory read
(IRx(15 downto 14) = "10") or
-- or ALU
(IRx(15 downto 14) = "11"))) then
-- or set
muxBSel <= DOUT;
elsif ((IRm(13 downto 11) = IRin(2 downto 0)) and
-- WRITE BACK
((IRm(15 downto 14) = "01" and IRm(5) = '0') or
-- memory read
(IRm(15 downto 14) = "10") or
-- or ALU
(IRm(15 downto 14) = "11"))) then
-- or set
muxBSel <= REGOUT;

else
dstalltemp <= xstall;
end if;
else
dstalltemp <= xstall;
end if;

if (IRin(15 downto 14) = "01" and IRin(5) = '1') then --if this
= MEM(write) (destination = val to write)
if (((IRtemp(13 downto 11) = IRin(13 downto 11)) and
((IRtemp(15 downto 14) = "01" and IRtemp(5) = '0') or
(IRtemp(15 downto 14) = "10") or
(IRtemp(15 downto 14) = "11"))) or
((IRx(13 downto 11) = IRin(13 downto 11)) and
((IRx(15 downto 14) = "01" and IRx(5) = '0') or
(IRx(15 downto 14) = "10") or
(IRx(15 downto 14) = "11"))) or
((IRm(13 downto 11) = IRin(13 downto 11)) and
((IRm(15 downto 14) = "01" and IRm(5) = '0') or
(IRm(15 downto 14) = "10") or
(IRm(15 downto 14) = "11")))) then
-- if out dest = this dest and out is doing a
MEM(read), ALU, SET op or
-- execute dest = this dest and execute is doing a
MEM(read), ALU, SET op or
-- memory dest = this dest and memory is doing a
MEM(read), ALU, SET op
dstalltemp <= '1';
invalid <= '1';
elsif write_flag = '0' then
dstalltemp <= '1';
else
dstalltemp <= xstall;
end if;
else
dstalltemp <= xstall;
end if;
else
dstalltemp <= xstall;
end if;
else
dstalltemp <= xstall;
invalid <= '1';
end if;
bsel <= IRin(2 downto 0);
if write_flag = '1' then -- insert 2nd write cycle
asel <= IRin(13 downto 11); -- data to be written
else
asel <= IRin(10 downto 8); --fetch register data
end if;
end process;
------code segment end-------------
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  #2 (permalink)  
Old 10-09-2003, 07:25 PM
MM
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Posts: n/a
Default Re: vhdl for data forwarding in a pipeline machine

For starters, you don't seem to have any default values for your muxes'
outputs:

> if finvalid = '0' then -- fetch out is valid
> dstalltemp <= xstall; -- set dstall to xstall (assume we will stall

if x is stalled)
> -- delayed branching segement
> if (IRin(15 downto 14) = "00" and IRin(11) = '0') then
> invalid <= bren; -- delete instruction after branch from pipe if not

a delayed branch
> end if;
> -- data forwarding segment
>
> if (IRin(15 downto 14) = "01" or IRin(15 downto 14) = "10") then
> if ((IRtemp(13 downto 11) = IRin(10 downto 8)) and --
> ((IRtemp(15 downto 14) = "01" and IRtemp(5) = '0') or --
> (IRtemp(15 downto 14) = "10") or --
> (IRtemp(15 downto 14) = "11"))) then --
> muxASel <= RESULT; --
> elsif ((IRx(13 downto 11) = IRin(10 downto 8)) and --
> ((IRx(15 downto 14) = "01" and IRx(5) = '0') or --
> (IRx(15 downto 14) = "10") or --
> (IRx(15 downto 14) = "11"))) then --
> muxASel <= DOUT; --
> elsif ((IRm(13 downto 11) = IRin(10 downto 8)) and --
> ((IRm(15 downto 14) = "01" and IRm(5) = '0') or --
> (IRm(15 downto 14) = "10") or --
> (IRm(15 downto 14) = "11"))) then --
> muxASel <= REGOUT;
> else
> dstalltemp <= xstall;
> end if;


What should happen to muxASel when all of these conditions are not
satisfied? You may want to add a default value right after the begin
statement, before all if's ...

/Mikhail


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