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Old 11-03-2006, 02:32 PM
yaveh (Yet Another Vhdl Engineer Hoping)
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Default VHDL-AMS: assert as simultaneous statement


Hi,

I consider good design practise to write case statements with a
default 'others' choice to be able to catch design errors and
properly mark them with an assert statement.

This works fine with VHDL sequentials and concurrent assert statements.

However, I canīt get VHDL-AMS simultaneous assert statement to work.
My tool complain with "unknown concurrent/simultaneous statement "
when I write, e.g.:

architecture [...] of [...] is
shared variable a : [...]
[...]
begin
[...]
case a use
when a1=> v'dot == -G - v**2*Air_Res; ;-- e.g.
when b2=> [...]
when others =>
assert false report "case defaulted!" severity failure;
end case;
end;

If you use VHDL-AMS, donīt you find it necessary?
I just canīt find thsi construct in the Quick Reference of several
VHDL-AMS Simulator...

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Old 11-27-2006, 10:17 PM
Paul Floyd
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Default Re: VHDL-AMS: assert as simultaneous statement

On 3 Nov 2006 05:32:51 -0800, yaveh (Yet Another Vhdl Engineer Hoping)
<[email protected]> wrote:
>
> Hi,
>
> I consider good design practise to write case statements with a
> default 'others' choice to be able to catch design errors and
> properly mark them with an assert statement.
>
> This works fine with VHDL sequentials and concurrent assert statements.
>
> However, I canīt get VHDL-AMS simultaneous assert statement to work.
> My tool complain with "unknown concurrent/simultaneous statement "
> when I write, e.g.:
>
> architecture [...] of [...] is
> shared variable a : [...]
> [...]
> begin
> [...]
> case a use
> when a1=> v'dot == -G - v**2*Air_Res; ;-- e.g.
> when b2=> [...]
> when others =>
> assert false report "case defaulted!" severity failure;
> end case;
> end;
>
> If you use VHDL-AMS, donīt you find it necessary?
> I just canīt find thsi construct in the Quick Reference of several
> VHDL-AMS Simulator...


I haven't checked in the LRM, but I don't think that this is allowed.

A somewhat ugly solution, which doesn't quite do what you want (but
might be good enough for simulation), might be to define a function that
contains an assert.

For instance

function my_assert(s: string) return [type of a1, b2 ...] is
begin
assert false report s severity failure;
return 0.0; -- or whatever is compatible with a1 ...
end;


case a use
when a1=> v'dot == -G - v**2*Air_Res; ;-- e.g.
when b2=> [...]
when others =>
dummy == my_assert("case defaulted!");
end case;

A bientot
Paul
(Not speaking for Mentor Graphics)
--
Paul Floyd http://paulf.free.fr (for what it's worth)
Surgery: ennobled Gerald.
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