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  #1 (permalink)  
Old 09-18-2003, 12:03 PM
Ahmad
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Default Type Error ??!! Any help

Hi all,

I hope any one can help me with this error. I get this eror everytime:

"cic_order3_testbench_struct.vhd",line 82: Error, type error at
'difout_2'. Needed type 'signed'.

I can't understand what this error is?!
Note: cic_order3 works alone, just be connecting its output to a port
in the testbench it gives this error


-- renoir header_start
--
-- VHDL Entity integrator.CIC_order3_TestBench.symbol
--
-- Created:
-- by - ahmad.UNKNOWN (KIMO-DESKTOP)
-- at - 13:00:30 18-Sep-03
--
-- Generated by Mentor Graphics' Renoir(TM) 2000.3 (Build 2)
--
-- renoir header_end
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY CIC_order3_TestBench IS
PORT(
Clk : IN std_logic ;
Reset : IN std_logic ;
combout : OUT signed (15 DOWNTO 0)
);

-- Declarations

END CIC_order3_TestBench ;

-- renoir interface_end
--
-- VHDL Architecture integrator.CIC_order3_TestBench.struct
--
-- Created:
-- by - ahmad.UNKNOWN (KIMO-DESKTOP)
-- at - 13:00:30 18-Sep-03
--
-- Generated by Mentor Graphics' Renoir(TM) 2000.3 (Build 2)
--
LIBRARY ieee ;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY std ;
USE std.textio.ALL;

LIBRARY integrator;

ARCHITECTURE struct OF CIC_order3_TestBench IS

-- Architecture declarations

-- Internal signal declarations
SIGNAL TRout : signed(15 downto 0);

-- Component Declarations
COMPONENT CIC_order3
PORT (
Clk : IN std_logic ;
IntIn : IN signed (15 downto 0);
Reset : IN std_logic ;
DifOut_2 : OUT signed (15 downto 0)
);
END COMPONENT;
COMPONENT TextReader
PORT (
Clk : IN std_logic ;
Reset : IN std_logic ;
TRout : OUT signed (15 downto 0)
);
END COMPONENT;

-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : CIC_order3 USE ENTITY integrator.CIC_order3;
FOR ALL : TextReader USE ENTITY integrator.TextReader;
-- pragma synthesis_on

BEGIN
-- Instance port mappings.
I0 : CIC_order3
PORT MAP (
Clk => Clk,
IntIn => TRout,
Reset => Reset,
DifOut_2 => combout --THIS IS THE ERROR
);
I1 : TextReader
PORT MAP (
Clk => Clk,
Reset => Reset,
TRout => TRout
);

END struct;
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  #2 (permalink)  
Old 09-18-2003, 12:45 PM
Allan Herriman
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Posts: n/a
Default Re: Type Error ??!! Any help

On 18 Sep 2003 03:03:01 -0700, [email protected] (Ahmad) wrote:

>Hi all,
>
>I hope any one can help me with this error. I get this eror everytime:
>
>"cic_order3_testbench_struct.vhd",line 82: Error, type error at
>'difout_2'. Needed type 'signed'.
>
>I can't understand what this error is?!
>Note: cic_order3 works alone, just be connecting its output to a port
>in the testbench it gives this error


[snip]

This seems to be the difference between
ieee.std_logic_arith.signed
and
ieee.numeric_std.signed

They're both "signed" but they're not the same as far as the compiler
is concerned.

Try changing one of the libraries, e.g. change
USE ieee.std_logic_arith.all;
to
USE ieee.numeric_std.ALL;

Regards,
Allan.
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  #3 (permalink)  
Old 09-18-2003, 12:57 PM
Eyck Jentzsch
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Posts: n/a
Default Re: Type Error ??!! Any help

Hi,
you use ieee.std_logic_arith in your entity and ieee.numeric_std in your
architecture. Both define a type 'signed' but VHDL treats them as
different, incompatible types (no implicit type conversion possible).
bye

-Eyck

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  #4 (permalink)  
Old 09-21-2003, 08:46 AM
Ahmad
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Posts: n/a
Default Re: Type Error ??!! Any help

Thnx for all the replies. It worked, pretty stupid though, the
compiler should warn me of 'signed type re-definition' or something!

Eyck Jentzsch <[email protected]> wrote in message news:<[email protected]>...
> Hi,
> you use ieee.std_logic_arith in your entity and ieee.numeric_std in your
> architecture. Both define a type 'signed' but VHDL treats them as
> different, incompatible types (no implicit type conversion possible).
> bye
>
> -Eyck

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