FPGA Central

hello
i am new to vhdl and xilinx. using tutorials i was able to use
corgen for generating a core for DPRAM,multiplication , summation etc.
in dpram coregen i specified the ".coe" file which will be loaded in
it during simulation.
my project reads the data from dpram1 processes it and saves it
to dpram2. how to write a testbench that will save the results being
stored in dpram in a file for viewing it ? or should i say how to read
the contents of dpram2 after simulation is over ?
i really need a good practical tutorial on testbench...till now i m
using testbench waveform part of xilinx ise.


regards
nisheeth

Nisheeth wrote:
> i am new to vhdl and xilinx. using tutorials i was able to use
> corgen for generating a core for DPRAM,multiplication , summation etc.
> in dpram coregen i specified the ".coe" file which will be loaded in
> it during simulation.

Coregen is the X-path to black-box design entry.
There is a similar A-path.
On these paths, an HDL netlist or a schematic
is used to wire up the black boxes.
Such netlists are sometimes loaded and tested by trial and error,
or tested using a waveform-based simulator.
The advantage to this path is that you can get
some work done without having to learn an HDL.
You can read all about this process on comp.arch.fpga

The alternative path is HDL synthesis and simulation.
Code written using standard synthesis templates
can generate equivalent logic, but can also be
tested *before* it is reduced to LUTS and flops
and even before a device is selected.
There is a reference design and testbench here:
http://home.comcast.net/~mike_treseler/
if you are interested in learning vhdl for synthesis
and simulation.

> my project reads the data from dpram1 processes it and saves it
> to dpram2. how to write a testbench that will save the results being
> stored in dpram in a file for viewing it ? or should i say how to read
> the contents of dpram2 after simulation is over ?

The purpose of a testbench is to verify that your
design module/entity responds to inputs exactly
as you expect. The simulator provides waveforms
for debugging, but the ultimate goal is a PASS/FAIL result.
Make the testbench do the work, so that you don't have to.

Good luck.

-- Mike Treseler