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Old 09-09-2003, 12:37 AM
Kelvin @ Singapore
Posts: n/a
Default Synthesizing a design with RAM.

Hi, all:

What is the right procedure to synthesize a design with a RAM when I don't
have a .db model for the
RAM? I only have the datasheet and .lib file generated from a RAM-Generator
supplied by the fab.

I could use Library Compiler to convert .lib into .db but with a warning
saying "LC is not enabled and
cell functionalities are ignored". Does this .db file include the timing
checks on the IO of the RAM or
just a black box with no functionality and no timing?

Best Regards,

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