FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > VHDL

VHDL comp.lang.vhdl newsgroup / Usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 09-09-2003, 12:37 AM
Kelvin @ Singapore
Guest
 
Posts: n/a
Default Synthesizing a design with RAM.

Hi, all:

What is the right procedure to synthesize a design with a RAM when I don't
have a .db model for the
RAM? I only have the datasheet and .lib file generated from a RAM-Generator
supplied by the fab.

I could use Library Compiler to convert .lib into .db but with a warning
saying "LC is not enabled and
cell functionalities are ignored". Does this .db file include the timing
checks on the IO of the RAM or
just a black box with no functionality and no timing?



Best Regards,
Kelvin








Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Synthesizing big RAMs Xin Xiao FPGA 7 01-12-2008 12:15 AM
Synthesizing fixed_pkg in ISE 9.2 Andreas Schwarz FPGA 10 08-28-2007 03:25 PM
Synthesizing ROM nezhate Verilog 3 05-07-2007 01:23 PM
using FPGAs for synthesizing? Frank Buss FPGA 2 11-11-2006 06:54 PM
Synthesizing for gates only Charles Bailey Verilog 6 12-02-2004 08:48 AM


All times are GMT +1. The time now is 06:22 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved