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Hello,

I have this quesiton - on writing a synthesis equivalent code -

Question on how to write a synthesis equivalent code in VHDL for the
below code -

Counter is a synchronous with Clock and has a synchro. reset inside.

************************************************** *******************************
signal CNT_OUT : unsigned ( 9 downto 0 );

begin

counter_dut : count1 ( clk => CLK,
reset => reset,
cntout => CNT_OUT );

---- this statement is what my question is about really
-- How does the synthesis engine interpret this statement.
-- is it okay to give a decimal integer value here on the right side of
the comparison ?


MISER_PLL_RESETN <= '1' when (CNT_OUT >= 50 and CNT_OUT <= 100) else

'0' ;

Appreciate any help / suggestions on this. Thanks.

Regards,
Rama

use to_integer() or conv_integer()

Regards,
JK

On Jan 17, 8:58 pm, "Rama" <[email protected]> wrote:
> Hello,
>
> I have this quesiton - on writing a synthesis equivalent code -
>
> Question on how to write a synthesis equivalent code in VHDL for the
> below code -
>
> Counter is a synchronous with Clock and has a synchro. reset inside.
>
> ************************************************** *******************************
> signal CNT_OUT : unsigned ( 9 downto 0 );
>
> begin
>
> counter_dut : count1 ( clk => CLK,
> reset => reset,
> cntout => CNT_OUT );
>
> ---- this statement is what my question is about really
> -- How does the synthesis engine interpret this statement.
> -- is it okay to give a decimal integer value here on the right side of
> the comparison ?
>
> MISER_PLL_RESETN <= '1' when (CNT_OUT >= 50 and CNT_OUT <= 100) else
>
> '0' ;
>
> Appreciate any help / suggestions on this. Thanks.
>
> Regards,
> Rama