FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > VHDL

VHDL comp.lang.vhdl newsgroup / Usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 09-19-2006, 08:49 AM
hema
Guest
 
Posts: n/a
Default switch controller design

hii all,

I have a doubt regarding the design of switch controller on
fpga,first of all the switch has nothing to do with the ip addresses,it
works on mac addresses,but when u connect systems to a switch we
access using the ip adresses.through ARP it will know the mac
adresses.Now my doubt is when implementing the switch on a fpga how
will i make it supportive to ARP.please let me know the details,and
also for the first time how does the switching table is built?????

regards,
hema.

Reply With Quote
  #2 (permalink)  
Old 09-19-2006, 06:19 PM
David Ashley
Guest
 
Posts: n/a
Default Re: switch controller design

hema wrote:
> hii all,
>
> I have a doubt regarding the design of switch controller on
> fpga,first of all the switch has nothing to do with the ip addresses,it
> works on mac addresses,but when u connect systems to a switch we
> access using the ip adresses.through ARP it will know the mac
> adresses.Now my doubt is when implementing the switch on a fpga how
> will i make it supportive to ARP.please let me know the details,and
> also for the first time how does the switching table is built?????
>
> regards,
> hema.
>


Assuming the switch is a layer II, it doesn't need to know anything but
the ethernet layer. ARP packets are sent to the ethernet broadcast
address (FF FF FF FF FF FF) when appropriate. The switch must
send all such packets to all ports. The devices plugged in need to deal
with ARP, not the switch itself.

The switch just looks at the source and destination MAC addresses.
If a packet comes in on port X from some source, the switch adds that
source to that port's list. So when a packet comes in with that MAC
addesss as a destination, it knows what port to send it to.

I think typical behavior if a switch doesn't know a port associated with
a destination MAC address is to just drop the packet. I suppose it could
also send it to all ports...

There is another issue, if there are loops in the way the ports are
wired up. Spanning tree protocol can be used to detect these. Most
cheap switches don't implement this.

-Dave


--
David Ashley http://www.xdr.com/dash
Embedded linux, device drivers, system architecture
Reply With Quote
  #3 (permalink)  
Old 09-19-2006, 06:37 PM
David Ashley
Guest
 
Posts: n/a
Default Re: switch controller design

David Ashley wrote:
> hema wrote:
>
>>hii all,
>>
>> I have a doubt regarding the design of switch controller on
>>fpga,first of all the switch has nothing to do with the ip addresses,it
>>works on mac addresses,but when u connect systems to a switch we
>>access using the ip adresses.through ARP it will know the mac
>>adresses.Now my doubt is when implementing the switch on a fpga how
>>will i make it supportive to ARP.please let me know the details,and
>>also for the first time how does the switching table is built?????
>>
>>regards,
>>hema.
>>

>
>
> Assuming the switch is a layer II, it doesn't need to know anything but
> the ethernet layer. ARP packets are sent to the ethernet broadcast
> address (FF FF FF FF FF FF) when appropriate. The switch must
> send all such packets to all ports. The devices plugged in need to deal
> with ARP, not the switch itself.
>
> The switch just looks at the source and destination MAC addresses.
> If a packet comes in on port X from some source, the switch adds that
> source to that port's list. So when a packet comes in with that MAC
> addesss as a destination, it knows what port to send it to.
>
> I think typical behavior if a switch doesn't know a port associated with
> a destination MAC address is to just drop the packet. I suppose it could
> also send it to all ports...
>
> There is another issue, if there are loops in the way the ports are
> wired up. Spanning tree protocol can be used to detect these. Most
> cheap switches don't implement this.
>
> -Dave
>
>


Another point. Multicast traffic is another complication. Multicast is
identified by certain ranges of IP addresses. It may be that a multicast
packet has a destination MAC address of all FF's. I've seen the el cheapo
switches bog down with multicast traffic, they just send it to all ports.
Instead there is a protocol where receivers join a multicast channel,
and so switches only need forward multicast packets if any of the ports
have any receivers attached. Otherwise it can safely drop them.

I'm wondering what sort of switch one would make with an FPGA.
If you're targeting the low end market, forget it -- $5 for a 5 port switch
good luck trying to create an fpga solution in that range. High end
I can see a point, say a big 40 port switch where all the ports are
connected to a big fpga and it's a 1G or 10G switch...in that case
you need to have external memory for storing packets. No FPGA would
have enough BRAMs to handle the storage requirements necessary...

But if it's high end it'll probably need to be a layer III switch + know
about
IP + routing + multicast...in other words it gets to be a lot more
complicated.

-Dave


--
David Ashley http://www.xdr.com/dash
Embedded linux, device drivers, system architecture
Reply With Quote
  #4 (permalink)  
Old 09-23-2006, 07:18 AM
hema
Guest
 
Posts: n/a
Default Re: switch controller design

hiiiii dave,

Thanks for your suggestion,give me some tips on how to
implement shared memory switch fabric and is a transceiver alone is
enough to make it work as a hub???
reply at the earliest.thank you.

regards,
hema.


David Ashley wrote:

> David Ashley wrote:
> > hema wrote:
> >
> >>hii all,
> >>
> >> I have a doubt regarding the design of switch controller on
> >>fpga,first of all the switch has nothing to do with the ip addresses,it
> >>works on mac addresses,but when u connect systems to a switch we
> >>access using the ip adresses.through ARP it will know the mac
> >>adresses.Now my doubt is when implementing the switch on a fpga how
> >>will i make it supportive to ARP.please let me know the details,and
> >>also for the first time how does the switching table is built?????
> >>
> >>regards,
> >>hema.
> >>

> >
> >
> > Assuming the switch is a layer II, it doesn't need to know anything but
> > the ethernet layer. ARP packets are sent to the ethernet broadcast
> > address (FF FF FF FF FF FF) when appropriate. The switch must
> > send all such packets to all ports. The devices plugged in need to deal
> > with ARP, not the switch itself.
> >
> > The switch just looks at the source and destination MAC addresses.
> > If a packet comes in on port X from some source, the switch adds that
> > source to that port's list. So when a packet comes in with that MAC
> > addesss as a destination, it knows what port to send it to.
> >
> > I think typical behavior if a switch doesn't know a port associated with
> > a destination MAC address is to just drop the packet. I suppose it could
> > also send it to all ports...
> >
> > There is another issue, if there are loops in the way the ports are
> > wired up. Spanning tree protocol can be used to detect these. Most
> > cheap switches don't implement this.
> >
> > -Dave
> >
> >

>
> Another point. Multicast traffic is another complication. Multicast is
> identified by certain ranges of IP addresses. It may be that a multicast
> packet has a destination MAC address of all FF's. I've seen the el cheapo
> switches bog down with multicast traffic, they just send it to all ports.
> Instead there is a protocol where receivers join a multicast channel,
> and so switches only need forward multicast packets if any of the ports
> have any receivers attached. Otherwise it can safely drop them.
>
> I'm wondering what sort of switch one would make with an FPGA.
> If you're targeting the low end market, forget it -- $5 for a 5 port switch
> good luck trying to create an fpga solution in that range. High end
> I can see a point, say a big 40 port switch where all the ports are
> connected to a big fpga and it's a 1G or 10G switch...in that case
> you need to have external memory for storing packets. No FPGA would
> have enough BRAMs to handle the storage requirements necessary...
>
> But if it's high end it'll probably need to be a layer III switch + know
> about
> IP + routing + multicast...in other words it gets to be a lot more
> complicated.
>
> -Dave
>
>
> --
> David Ashley http://www.xdr.com/dash
> Embedded linux, device drivers, system architecture


Reply With Quote
  #5 (permalink)  
Old 09-23-2006, 06:07 PM
David Ashley
Guest
 
Posts: n/a
Default Re: switch controller design

hema wrote:
> hiiiii dave,
>
> Thanks for your suggestion,give me some tips on how to
> implement shared memory switch fabric and is a transceiver alone is
> enough to make it work as a hub???
> reply at the earliest.thank you.
>
> regards,
> hema.


Regarding a hub, I think all ports on the hub are wired
together in some way, since collisions can occur. But I
don't know details. Regarding your other question, I have
no idea how to answer. Usually one conceives of an
overall architecture for a solution, then breaks it up
into pieces, then tackles each one until the job is done.
I don't think you can count on a newsgroup for doing your
entire job for you . General tips + theory are possible.

-Dave

--
David Ashley http://www.xdr.com/dash
Embedded linux, device drivers, system architecture
Reply With Quote
  #6 (permalink)  
Old 09-23-2006, 10:28 PM
Kai Harrekilde-Petersen
Guest
 
Posts: n/a
Default Re: switch controller design

David Ashley <[email protected]> writes:

> hema wrote:
>>
>> Thanks for your suggestion,give me some tips on how to
>> implement shared memory switch fabric and is a transceiver alone is
>> enough to make it work as a hub???
>> reply at the earliest.thank you.

>
> Regarding a hub, I think all ports on the hub are wired
> together in some way, since collisions can occur.


As far as I know, correct. In Ethernet, all the PHY's in a hub are
logically connected to a shared bus, and traffic on more than one port
results in a collision on the bus and hence on the ports.

As for shared-memory switch fabric design, I suggest you (ie: hema)
look up some books on the subject, go hunting on the websites of
companies such as broadcom, marvell, and vitesse, look in the patent
litterature, and in conference proceedings. That should provide you
with plenty of leads.


Kai
--
Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>
Reply With Quote
  #7 (permalink)  
Old 09-23-2006, 10:32 PM
Kai Harrekilde-Petersen
Guest
 
Posts: n/a
Default Re: switch controller design

"hema" <[email protected]> writes:

> hii all,
>
> I have a doubt regarding the design of switch controller on
> fpga,first of all the switch has nothing to do with the ip addresses,it
> works on mac addresses,but when u connect systems to a switch we
> access using the ip adresses.through ARP it will know the mac
> adresses.Now my doubt is when implementing the switch on a fpga how
> will i make it supportive to ARP.please let me know the details,and
> also for the first time how does the switching table is built?????


Normally, a L2 switch won't listen/participate in ARP (only advanced
switch/routers do this). ARP translates from L3 (IP) addresses to L2
(MAC) addresses.

If all you want is to learn where your L2 addresses are, the standard
solution is "backward learning". Google is your friend:
http://www.google.com/search?hl=en&q=backward+learning

Regards,


Kai
--
Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>
Reply With Quote
  #8 (permalink)  
Old 10-09-2006, 11:39 AM
hema
Guest
 
Posts: n/a
Default Re: switch controller design

hiiii,

In case of designing the switch controller on FPGA ,how to resolve the
contention when all the input buffers(FIFO) try out for the same output
FIFO????

regards,
hema.
Kai Harrekilde-Petersen wrote:
> "hema" <[email protected]> writes:
>
> > hii all,
> >
> > I have a doubt regarding the design of switch controller on
> > fpga,first of all the switch has nothing to do with the ip addresses,it
> > works on mac addresses,but when u connect systems to a switch we
> > access using the ip adresses.through ARP it will know the mac
> > adresses.Now my doubt is when implementing the switch on a fpga how
> > will i make it supportive to ARP.please let me know the details,and
> > also for the first time how does the switching table is built?????

>
> Normally, a L2 switch won't listen/participate in ARP (only advanced
> switch/routers do this). ARP translates from L3 (IP) addresses to L2
> (MAC) addresses.
>
> If all you want is to learn where your L2 addresses are, the standard
> solution is "backward learning". Google is your friend:
> http://www.google.com/search?hl=en&q=backward+learning
>
> Regards,
>
>
> Kai
> --
> Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>


Reply With Quote
  #9 (permalink)  
Old 10-09-2006, 07:24 PM
Mike Treseler
Guest
 
Posts: n/a
Default Re: switch controller design

hema wrote:

> In case of designing the switch controller on FPGA ,how to resolve the
> contention when all the input buffers(FIFO) try out for the same output
> FIFO????


Choose a winner and lock out the others.

-- Mike Treseler
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
RS-232 Bus controller design in VHDL ikki FPGA 19 11-10-2008 07:59 PM
Memory controller design Piotr Wyderski FPGA 7 01-03-2007 11:35 AM
Help in controller design srinukasam VHDL 0 09-09-2005 12:39 PM
Motion controller design with CPLD Leeinhyuk FPGA 1 06-09-2005 10:06 AM
Motion controller design with CPLD Leeinhyuk FPGA 0 06-09-2005 08:52 AM


All times are GMT +1. The time now is 04:13 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved