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Old 11-01-2003, 06:02 PM
Valentin Tihomirov
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Default Structural VHDL - Accesing signals of instances

I understand that entity defines inteface restricting the range of signals
available for communication with instances of that entity. May be there is
no much sense to bypass the restriction but I consider this opportunity to
be used in test bench.


uut: entity UART port map (
.....
);

--stimulate uart


--wait until transmitter is empty
wait until uut.transmitter.busy = '0';

-- go on



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Old 11-01-2003, 08:21 PM
Jim Lewis
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Default Re: Structural VHDL - Accesing signals of instances

If you are using ModelSim, you can use the
signal spy package.

Cheers,
Jim

Valentin Tihomirov wrote:

> I understand that entity defines inteface restricting the range of signals
> available for communication with instances of that entity. May be there is
> no much sense to bypass the restriction but I consider this opportunity to
> be used in test bench.
>
>
> uut: entity UART port map (
> ....
> );
>
> --stimulate uart
>
>
> --wait until transmitter is empty
> wait until uut.transmitter.busy = '0';
>
> -- go on
>
>
>


--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~

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  #3 (permalink)  
Old 11-02-2003, 01:08 PM
Paul Uiterlinden
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Default Re: Structural VHDL - Accesing signals of instances

Valentin Tihomirov wrote:

> I understand that entity defines inteface restricting the range of
> signals available for communication with instances of that entity.
> May be there is no much sense to bypass the restriction but I
> consider this opportunity to be used in test bench.


Declare the signals you want to observe in a package and "use" that
package both in the DUT and testbench. See also
http://www.eda.org/comp.lang.vhdl/FAQ1.html#monitor

Paul.
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