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Old 10-26-2006, 11:13 AM
Christian Kraemer
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Default Strange signal behaviour

Hello everyone,

I encountered a very strange singnal behaviour. I will try to sketch
out the facts as precisely as possible:

I am interfacing an FPGA (Virtex2) chip with an external IC interface
(Philips PCA9564). I can send commands to the PCA9564, for which I have
to wait until they are completed. The PCA9564 features an active low
INT signal which tells me that a transaction on the bus has been
completed. This INT signal is checked noumerous times in my VHDL code.
Now this check reproducibly fails after only a few checks, which means
e.g. the tenth time I have to wait for INT = 0 (which means to cycle on
the INT = 0 condition), my VHDL code does cycle forever.

I looked into this with a digital/analog oscilloscope (I am a student,
and the university features some very nice hardware), and noted, that
the analog INT signal indeed drop to a low level - as well as the
digitalized signal that I for debug reasons routed to the outside and
checked with a digital probe.

So as far as I can see, all needed conditions are met.

After some trying around, I changed the way the signal is read. Now,
instead of reading the port signal directly wherever needed, I added a
process and an internal signal (pca9564_int is the external signal from
the chip):

pca9564_interrupt <= pca9564_int WHEN clock'EVENT AND clock = '1';

In my understanding, this should lead to an additional register in
synthesis. So now my code checks on the register value. And to my
surprise, this works like a charm ...

Now, so there is isn't really a problem here, since everything works
fine.
Yet I am courious why this is working. So has anyone an idea why my
initial setup didn't work, and why it does work with the extra process?

Could this be because of a fanout problem when accessing the external
signal directly - and shouldn't the synthesis tool prevent this?

Thanks for any oppinion provided.

Christian Kraemer

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Old 10-26-2006, 12:40 PM
Peter
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Default Re: Strange signal behaviour


Christian Kraemer skrev:

> Hello everyone,
>
> I encountered a very strange singnal behaviour. I will try to sketch
> out the facts as precisely as possible:
>
> Yet I am courious why this is working. So has anyone an idea why my
> initial setup didn't work, and why it does work with the extra process?
>


Hi,

Every asynchronous signal which goes into a synchronous system needs to
be synchronized using registers. A single register may be insufficient
to provide a reliable system. You may need two or even three registers
to decrease the propability of metastability.
Without a synchronizer, some parts of your design may read the input as
low while others read it as high, if it's read when it's changing. That
may lead to very interesting behaviour...

/Peter

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Old 10-28-2006, 09:54 AM
mysticlol
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Default Re: Strange signal behaviour

check this thread..
http://groups.google.com/group/comp....8d231476233bd6

regards,
Krishna Janumanchi

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