 |
FPGA CentralWorld's 1st FPGA Portal |
|
|
|
|||||||
| VHDL comp.lang.vhdl newsgroup / Usenet |
|
|
|
 |
|
|
LinkBack | Thread Tools | Display Modes |
06-28-2005, 04:13 PM
|
|||
|
|||
Specifying vector length in the function output
it seems that the following code will not work
function F() return std_logic_vector (1 to 10) -- error while the following is compiled function F() return std_logic_vector So, I would like to highlight the length to the user looking at package interface part. 
|
|
06-28-2005, 07:52 PM
|
|||
|
|||
|
Re: Specifying vector length in the function output
"valentin tihomirov" <[email protected]> writes:
> it seems that the following code will not work > > function F() return std_logic_vector (1 to 10) -- error [...] > So, I would like to highlight the length to the user looking at package > interface part. Just define a subtype. HTH, Colin
|
|
| Bookmarks |
Linear Mode
|
|
Similar Threads
|
||||
| Thread | Thread Starter | Forum | Replies | Last Post |
| How do i pass a real function to the output port | shwetika | Verilog | 2 | 06-06-2008 06:18 AM |
| Need standard function to do (Bool and Vector) | Weng Tianxiang | VHDL | 2 | 06-21-2005 01:01 AM |
| How to use file input output function? | Jasmine Hau | FPGA | 0 | 02-16-2005 02:50 AM |
| How to handle varied length of output signal | systolic | VHDL | 3 | 10-21-2004 10:03 PM |
| huh?? compare problem with vector length?? | JT | Verilog | 3 | 10-24-2003 03:19 PM |
All times are GMT +1. The time now is 11:56 AM.
