Re: Simulation problem in VHDL Simili from Symphony EDA package.
You've just hit upon the main reason not to use such simulator commands
for stimulus: they're not portable between different simulators!
Better to stimulte from a vhdl testbench wrapper around your
unit-under-test, with a signal assignment such as:
signal clk : std_logic := '1'; -- init val is ok for sim!
signal stop : boolean := false;
constant clk_prd : time : 10 ns; -- change as requiresd
constant sim_time : time := 100 * clk_prd; -- change as required
....
clk <= not clk after clk_prd / 2 when not stop;
stop <= true after sim_time; -- stop clock
This will work from any vhdl simulator.
Andy
Daniel wrote:
> How do I simulate CLOCK signal?
>
> I'm previous user of ActiveHDL where I could simply choose "stimulators" -
> clk, hotkey, forse '0', '1',...
>
> I can't find anything like this in VHDL Simili's Sonata simulator.
>
> Do I have to write a code for CLK signal? I read the official docs, but
> couldn't find any information about this,...
>
> Thanks.
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