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Old 10-17-2006, 08:48 AM
Daniel
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Default Simulation problem in VHDL Simili from Symphony EDA package.

How do I simulate CLOCK signal?

I'm previous user of ActiveHDL where I could simply choose "stimulators" -
clk, hotkey, forse '0', '1',...

I can't find anything like this in VHDL Simili's Sonata simulator.

Do I have to write a code for CLK signal? I read the official docs, but
couldn't find any information about this,...

Thanks.


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  #2 (permalink)  
Old 10-17-2006, 05:14 PM
Ajeetha
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Default Re: Simulation problem in VHDL Simili from Symphony EDA package.

Your best bet will be to write one line code inside your "testbench"
as:

signal clock : std_logic := '0';
.....
clock <= not clock after 10 ns;

HTH
Ajeetha, CVC
www.noveldv.com

Daniel wrote:
> How do I simulate CLOCK signal?
>
> I'm previous user of ActiveHDL where I could simply choose "stimulators" -
> clk, hotkey, forse '0', '1',...
>
> I can't find anything like this in VHDL Simili's Sonata simulator.
>
> Do I have to write a code for CLK signal? I read the official docs, but
> couldn't find any information about this,...
>
> Thanks.


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  #3 (permalink)  
Old 10-18-2006, 05:28 PM
Andy
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Default Re: Simulation problem in VHDL Simili from Symphony EDA package.

You've just hit upon the main reason not to use such simulator commands
for stimulus: they're not portable between different simulators!

Better to stimulte from a vhdl testbench wrapper around your
unit-under-test, with a signal assignment such as:

signal clk : std_logic := '1'; -- init val is ok for sim!
signal stop : boolean := false;
constant clk_prd : time : 10 ns; -- change as requiresd
constant sim_time : time := 100 * clk_prd; -- change as required
....
clk <= not clk after clk_prd / 2 when not stop;

stop <= true after sim_time; -- stop clock

This will work from any vhdl simulator.

Andy


Daniel wrote:
> How do I simulate CLOCK signal?
>
> I'm previous user of ActiveHDL where I could simply choose "stimulators" -
> clk, hotkey, forse '0', '1',...
>
> I can't find anything like this in VHDL Simili's Sonata simulator.
>
> Do I have to write a code for CLK signal? I read the official docs, but
> couldn't find any information about this,...
>
> Thanks.


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  #4 (permalink)  
Old 10-18-2006, 09:19 PM
pitarda
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Default Re: Simulation problem in VHDL Simili from Symphony EDA package.

I will take you advice and try to write the code this way.

Thanks.


Andy je napisal:
> You've just hit upon the main reason not to use such simulator commands
> for stimulus: they're not portable between different simulators!
>
> Better to stimulte from a vhdl testbench wrapper around your
> unit-under-test, with a signal assignment such as:
>
> signal clk : std_logic := '1'; -- init val is ok for sim!
> signal stop : boolean := false;
> constant clk_prd : time : 10 ns; -- change as requiresd
> constant sim_time : time := 100 * clk_prd; -- change as required
> ...
> clk <= not clk after clk_prd / 2 when not stop;
>
> stop <= true after sim_time; -- stop clock
>
> This will work from any vhdl simulator.
>
> Andy
>
>
> Daniel wrote:
> > How do I simulate CLOCK signal?
> >
> > I'm previous user of ActiveHDL where I could simply choose "stimulators" -
> > clk, hotkey, forse '0', '1',...
> >
> > I can't find anything like this in VHDL Simili's Sonata simulator.
> >
> > Do I have to write a code for CLK signal? I read the official docs, but
> > couldn't find any information about this,...
> >
> > Thanks.


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