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Old 09-27-2006, 02:46 PM
Mounard le Fougueux
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Default Simplex in VHDL/FPGA


I'm need to implement a simplex linear programming solution in an
FPGA/VHDL. The object is to take blocks of data samplse from an ADC and
solve a linear cost + linear constraints classical Lin-Prog for each block.

my focus of interest is in ultimately doing this in an FPGA/ASIC - not
in a processor or group of processors.

If you have looked into this before, please let me know what you think!
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