FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > VHDL

VHDL comp.lang.vhdl newsgroup / Usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 09-26-2003, 09:50 AM
Don
Guest
 
Posts: n/a
Default Silly question....

Sorry for this silly question, but the issue bugs me a little.
I have the logical expression:

/A*/B + A*B

( / means not...)

could'nt this expression be reducved more????

Don


Reply With Quote
  #2 (permalink)  
Old 09-26-2003, 10:45 AM
Allan Herriman
Guest
 
Posts: n/a
Default Re: Silly question....

On Fri, 26 Sep 2003 10:50:05 +0200, "Don" <[email protected]> wrote:

>Sorry for this silly question, but the issue bugs me a little.
>I have the logical expression:
>
>/A*/B + A*B
>
>( / means not...)
>
>could'nt this expression be reducved more????


I translate this to VHDL (it *is* comp.lang.vhdl, after all) as

(not a and not b) or (a and b)

Is this what you meant?

It is equivalent to (a xnor b)

If your target hardware is lookup table based, then this already
produces the smallest amount of logic (1 LUT).
If your target hardware has an XNOR (or XOR) cell, it will probably be
smaller than the separate ANDs, OR and NOTs.
If you are making this out of transistors, there are some tricks you
can pull. I can get it down to 8 transistors after a few seconds
thought (two inverters and two transmission gates).

Was this homework?

Regards,
Allan.
Reply With Quote
  #3 (permalink)  
Old 09-26-2003, 12:38 PM
Don
Guest
 
Posts: n/a
Default Re: Silly question....

"Allan Herriman" <[email protected]> wrote in
message news:[email protected]...
> On Fri, 26 Sep 2003 10:50:05 +0200, "Don" <[email protected]> wrote:
>
> >Sorry for this silly question, but the issue bugs me a little.
> >I have the logical expression:
> >
> >/A*/B + A*B
> >
> >( / means not...)
> >
> >could'nt this expression be reducved more????

>
> I translate this to VHDL (it *is* comp.lang.vhdl, after all) as
>
> (not a and not b) or (a and b)
>
> Is this what you meant?
>
> It is equivalent to (a xnor b)
>
> If your target hardware is lookup table based, then this already
> produces the smallest amount of logic (1 LUT).
> If your target hardware has an XNOR (or XOR) cell, it will probably be
> smaller than the separate ANDs, OR and NOTs.
> If you are making this out of transistors, there are some tricks you
> can pull. I can get it down to 8 transistors after a few seconds
> thought (two inverters and two transmission gates).
>
> Was this homework?
>
> Regards,
> Allan.


Thank you very much.

Don


Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Beginner's silly question about ICAP [email protected] FPGA 3 04-04-2008 09:23 AM
clock problem --I new to this field so if question is silly don't mind badari FPGA 0 02-07-2006 06:19 AM
Silly Xilinx Foundation question... Nicholas Weaver FPGA 0 11-05-2004 10:13 PM
Silly ML300 question... Nicholas C. Weaver FPGA 0 11-04-2003 06:42 PM


All times are GMT +1. The time now is 11:56 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2024, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved