FPGA Central

Hi,

Im working on a structural rs latch model but the q and nq initial
values are wrong. When I tried to assign '0' and '1' initial values for
x_q and x_nq in the architecture declaration the simulator got in an
infinite loop. How can modify this model to reflect the correct
beginning values of q and nq?


LIBRARY ieee;
use ieee.std_logic_1164.all;

ENTITY rslatch IS
PORT( s, r : IN std_logic;
q, nq : OUT std_logic);
END rslatch;

ARCHITECTURE a OF rslatch IS
signal x_q: std_logic;
signal x_nq: std_logic;
BEGIN
x_q <= r nor x_nq;
x_nq <= s nor x_q;

nq <= x_nq;
q <= x_q;
END a;


Thanks
Attila

Attila Csosz wrote:

> Im working on a structural rs latch model but the q and nq initial
> values are wrong.

http://groups.google.com/groups/sear...29%22+practice

I need the (this) structural model for some reason.

Thanks
Attila



Mike Treseler wrote:
> Attila Csosz wrote:
>
>> Im working on a structural rs latch model but the q and nq initial
>> values are wrong.
>
> http://groups.google.com/groups/sear...29%22+practice
>