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Old 09-03-2005, 03:31 AM
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Default read hex file in VHDL using modelsim

Hi ,

I have a difficulty when I wants to read out hex format file in
vhdl. what's the best way to do? (I am using modelsim). An example of
my file is like this:




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  #2 (permalink)  
Old 09-03-2005, 06:37 PM
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Default Re: read hex file in VHDL using modelsim

Try using hread procedure (I believe it is part of
ieee.std_logic_textio for slv data type). Refer to VHDL FAQ for basic

4.2.12 How to Use Package Textio for Accessing Text Files


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Old 09-04-2005, 11:17 AM
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Default Re: read hex file in VHDL using modelsim

> (I am using modelsim)

In my opinion, that should not make a difference. ModelSim is only a
simulator and compiler software. The language constructs you use are
native to VHDL and will work on any simulator. Probably the only thing
you should check is which VHDL version your ModelSim supports.

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  #4 (permalink)  
Old 09-06-2005, 06:12 PM
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Default Re: read hex file in VHDL using modelsim

I would expect simulators to handle data based on their own formats
which could make each one different. I know that modelsim will read
std_logic from a binary file if it is coded x"03" for a '1' and x"02"
for a '0'. If that same file were read as a bit_vector the x"03"
would be x"03", not '1'. I doubt that x"03" is a standard for all
simulators trying to ready a binary file of stand logic data. Correct
me if this assumption is wrong please.

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