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Old 10-26-2003, 07:26 PM
Neil Zanella
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Default Re: unused wires and VHDL architectures


Peter Molesworth <[email protected]> wrote in message

> You could just create a signal to attach to the unused inputs and assign
> to this signal a default value. The synthesis/place&route tools will still
> optimize out the unused logic but won't complain about unused inputs.
> For example:
>
> architecture arch of Foo is
> -- declarations here
> signal FoosB : std_logic_vector (4 downto 1) := (others => '0');
> signal Gnd : std_logic := '0';
>
> begin
>
> U1 : Mux74x157
> port map (
> G => FoosG,
> S => Gnd,
> A => FoosA,
> B => FoosB, -- Unused inputs assigned to "0000"
> Y => FoosY
> );
>
> end arch;


This works but is somewhat misleading. Someone reading the design could be
erroneously misled into thinking that the signals FoosB and Gnd are
actually used for something when in fact they don't serve any particular
purpose other than bypassing the compiler warnings.

> Similarly for unused outputs VHDL provides the ability to specify the
> ports as 'open' in the component instantiation. For example:
>
> U1 : DFF
> port map (
> Clk => ClkIn,
> Clr => Clear,
> D => DataIn,
> Q => DataOut,
> nQ => open -- nothing gets attached here
> );


I wonder whether this works for inputs too. After all, there could be
inputs that under certain combinations of other inputs play no role in
determining the outputs. In this case it seems the design would be better
documented if the keyword open was used for such inputs as well. As I
understand it the open keyword may also be used for inputs as well so long
as default values are provided for the inputs in the port part of the
entity declaration.

> Note that this only works for whole ports and not parts of ports so if
> in your code above you wanted to only use 2 bits of Y then you would still
> have to assign all 4 bits to a signal as open could not be used.


The problem is that when the four bit signal is connected to another
component X and that component X does not use all four bits the compiler
complains. So there is no elegant way to get rid of that warning just
because I am using an std_ulogic_vector instead of four std_ulogic
signals?

Thanks,

Neil

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  #2 (permalink)  
Old 10-27-2003, 12:32 AM
David R Brooks
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Posts: n/a
Default Re: unused wires and VHDL architectures

Comments below...

Neil Zanella <[email protected]> wrote:

:
:Peter Molesworth <[email protected]> wrote in message
:
:> You could just create a signal to attach to the unused inputs and assign
:> to this signal a default value. The synthesis/place&route tools will still
:> optimize out the unused logic but won't complain about unused inputs.
:> For example:
:>
:> architecture arch of Foo is
:> -- declarations here
:> signal FoosB : std_logic_vector (4 downto 1) := (others => '0');
:> signal Gnd : std_logic := '0';
:>
:> begin
:>
:> U1 : Mux74x157
:> port map (
:> G => FoosG,
:> S => Gnd,
:> A => FoosA,
:> B => FoosB, -- Unused inputs assigned to "0000"
:> Y => FoosY
:> );
:>
:> end arch;
:
:This works but is somewhat misleading. Someone reading the design could be
:erroneously misled into thinking that the signals FoosB and Gnd are
:actually used for something when in fact they don't serve any particular
urpose other than bypassing the compiler warnings.

Just use a more meaningful dummy signal name, eg "unused_inputs".
:
:> Similarly for unused outputs VHDL provides the ability to specify the
:> ports as 'open' in the component instantiation. For example:
:>
:> U1 : DFF
:> port map (
:> Clk => ClkIn,
:> Clr => Clear,
:> D => DataIn,
:> Q => DataOut,
:> nQ => open -- nothing gets attached here
:> );
:
:I wonder whether this works for inputs too. After all, there could be
:inputs that under certain combinations of other inputs play no role in
:determining the outputs. In this case it seems the design would be better
:documented if the keyword open was used for such inputs as well. As I
:understand it the open keyword may also be used for inputs as well so long
:as default values are provided for the inputs in the port part of the
:entity declaration.
:
You can't have "open" inputs, because floating inputs in logic are a
Bad Thing. In practice, you would always tie those unused inputs to
something: VHDL just requires you tell it so.

:> Note that this only works for whole ports and not parts of ports so if
:> in your code above you wanted to only use 2 bits of Y then you would still
:> have to assign all 4 bits to a signal as open could not be used.
:
:The problem is that when the four bit signal is connected to another
:component X and that component X does not use all four bits the compiler
:complains. So there is no elegant way to get rid of that warning just
:because I am using an std_ulogic_vector instead of four std_ulogic
:signals?
:
But you can still connect the full-width vector to a named signal,
then rip the bits you need from that signal as inputs to another
component. Again, think hardware. That 4-bit vector is a 4-pin output
socket: you choose to wire only 3 of the pins. That's what you say in
VHDL. The full-width signal effectively names the plug that goes in
that socket (must be 4-pin, to mate with it): then you rip the lines
you actually use.

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