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  #1 (permalink)  
Old 06-24-2003, 11:40 AM
Troels Smit
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Default Re: event in state machine

Ralf Hildebrandt <[email protected]> wrote in message news:<[email protected]>...
> Hi Troels!
>
>
> > I have to change state on the event change of a signal - so I wrote
> > the following posted below.
> >
> > when wait4lr =>
> > if lr'event then
> > next_state <= wait20sclk_and4_cordic;
> > end if;
> >
> > This give a bad synchronous description of my "next_state" signal.

>
>
> if lr'event then
>
> is (nearly) the same like
>
> if (rising_edge(lr) OR falling_edge(lr)) then
>
>
> This "dual-edge-flipflop" is not synthesizable.
> Furthermore It's not recommended to put rising_edge / falling_edge in a
> branch of a case-statement.
>


Well, you are right that this way of writing dual edge triggered code
does not work ... but it is possible.
I found that the following code indeed will synthesize, you will find
dual edge, and case sentenze mixed terribly, but it synthesizes and I
don't see the difference between what I posted yesterday and the test
code below:


case test3 is
when '1' =>
if (clk'event) then
if (clk='1') then
test <= '0';
else
test <= '1';
end if;
end if;
when others =>
null;
end case;


if (reset='1') then
test3 <= '0';
elsif (reset'event and reset='0') then
test3 <= '1';
end if;
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  #2 (permalink)  
Old 06-24-2003, 02:17 PM
dbtid
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Default Re: event in state machine

On 24 Jun 2003 02:40:21 -0700, Troels Smit <[email protected]> wrote:

> Ralf Hildebrandt <[email protected]> wrote in message
> news:<[email protected]>...
>> Hi Troels!
>>
>>
>> > I have to change state on the event change of a signal - so I wrote
>> > the following posted below.
>> > > when wait4lr =>
>> > if lr'event then
>> > next_state <= wait20sclk_and4_cordic;
>> > end if;
>> > > This give a bad synchronous description of my "next_state" signal.

>>
>>
>> if lr'event then
>>
>> is (nearly) the same like
>>
>> if (rising_edge(lr) OR falling_edge(lr)) then
>>
>>
>> This "dual-edge-flipflop" is not synthesizable.
>> Furthermore It's not recommended to put rising_edge / falling_edge in a
>> branch of a case-statement.
>>

>
> Well, you are right that this way of writing dual edge triggered code
> does not work ... but it is possible.
> I found that the following code indeed will synthesize, you will find
> dual edge, and case sentenze mixed terribly, but it synthesizes and I
> don't see the difference between what I posted yesterday and the test
> code below:
>
>
> case test3 is
> when '1' =>
> if (clk'event) then
> if (clk='1') then
> test <= '0';
> else
> test <= '1';
> end if;
> end if;
> when others =>
> null;
> end case;


this is more like

test <= not clk;

[snip]


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  #3 (permalink)  
Old 06-25-2003, 03:38 PM
Mario Trams
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Default Re: event in state machine

Troels Smit wrote:

> When in a state, why is it not ok to listen for an event of another
> signal ??


Let me reverse your question: Assume you have a regular synchronous
state machine and you instantaneously want to change the state when
an event on some signal occured.
How would you create some piece of hardware using D-FlipFlops and
some logic gates that do the job?

Regards,
Mario
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  #4 (permalink)  
Old 06-25-2003, 08:03 PM
Pieter Hulshoff
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Default Re: event in state machine

Mario Trams wrote:
> Troels Smit wrote:
>> When in a state, why is it not ok to listen for an event of another
>> signal ??

> Let me reverse your question: Assume you have a regular synchronous
> state machine and you instantaneously want to change the state when
> an event on some signal occured.
> How would you create some piece of hardware using D-FlipFlops and
> some logic gates that do the job?


I think this is a better question indeed. Please describe what you wish
to create, and I'll see if I can give you some code that'll do it. What
Mario is describing is pretty easy to build in VHDL, so if you can give a
proper description of what you want, I'll see what I can do for you.

Kind regards,

Pieter Hulshoff

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  #5 (permalink)  
Old 06-25-2003, 08:04 PM
Mike Treseler
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Default Re: event in state machine



Troels Smit wrote:

>
> When in a state, why is it not ok to listen for an event of another signal ??


For simulation, that would work. It's legal VHDL.

For synthesis you should use the synchronous template.
The only event in synthesis is the rising edge of the clock.
Other "events" become synchronous strobes
Clock inputs to the dflops are not used for
any signal other than clk.

_|___|___|__ clk'event
_________________
______________/ my_output
___
_______________/ \__ my_event

-- Mike Treseler

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  #6 (permalink)  
Old 06-26-2003, 09:59 AM
Troels Smit
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Default Re: event in state machine

What is the "synchronous template" ??

I would like to make sure that Im doing this the easiest way:

What I need is to interface the DAC AK4520A. It has three control
signals "MCLK", "SCLK" and "LRCK".

These signals are connected to my clk as follows (counter is
incremented on each clk cyclk)

sclk <= counter(2);
mclk <= counter(0);
lr <= counter(8);

Now, on an LR'event I would like to send a serial word on the next 20
sclk'cycles, and then wait for the next lr'event.

How would you write that in VHDL ?
(You have a parallel serial converter with enable at your disposal,
giving data with sclk speed)

Best Regards,
Troels Smit

Mike Treseler <[email protected]> wrote in message news:<[email protected]>...
> Troels Smit wrote:
>
> >
> > When in a state, why is it not ok to listen for an event of another signal ??

>
> For simulation, that would work. It's legal VHDL.
>
> For synthesis you should use the synchronous template.
> The only event in synthesis is the rising edge of the clock.
> Other "events" become synchronous strobes
> Clock inputs to the dflops are not used for
> any signal other than clk.
>
> _|___|___|__ clk'event
> _________________
> ______________/ my_output
> ___
> _______________/ \__ my_event
>
> -- Mike Treseler

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  #7 (permalink)  
Old 06-26-2003, 07:20 PM
Mike Treseler
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Default Re: event in state machine

Troels Smit wrote:

> What is the "synchronous template" ??

see:
http://groups.google.com/groups?q=vh...late+spaghetti

> What I need is to interface the DAC AK4520A. It has three control
> signals "MCLK", "SCLK" and "LRCK".
>
> These signals are connected to my clk as follows (counter is
> incremented on each clk cyclk)
>
> sclk <= counter(2);
> mclk <= counter(0);
> lr <= counter(8);
>
> Now, on an LR'event I would like to send a serial word on the next 20
> sclk'cycles, and then wait for the next lr'event.
>
> How would you write that in VHDL ?

--------------------------------

I would write a process using the synchronous template.
Lets say your fpga clock is 40MHz and your generated
mclk is 10MHz. Now the process can generate clocks
or controls for the other inputs with a 50nS resolution.

A shift register with enable can drive the serial data.

To generate synchronous events, consider
using a procedure call like ck_rising(lr, last_lr, lr_rising);
by first declaring the functions below.

-- Mike Treseler

-------------------------

function now_high (std_arg : std_ulogic) -- input bit
return boolean is begin
if std_arg = '1' then return true;
else return false;
end if;
end function now_high;

procedure ck_rising(watch : in std_ulogic;
last_low : inout boolean;
result : out boolean)
is begin
result := now_high(watch) and last_low;
-- check for active edge based on

-- variable from last time;
last_low := now_low(watch);
-- assign variable for next time



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  #8 (permalink)  
Old 06-30-2003, 12:25 PM
Troels Smit
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Default Re: event in state machine

> PROCESS
> BEGIN
> WAIT UNTIL sclk = '1';
> lr_1d <= lr;
> lr_2d <= lr_1d;
> lr_3d <= lr_2d;
> END PROCESS;
>
> Now you can use lr_2d and lr_3d within a process to detect an event:
>
> PROCESS
> BEGIN
> WAIT UNTIL sclk = '1';
> IF lr_2d /= lr_3d THEN
> -- do your things
> END IF;
> END PROCESS;
>
> Using a process similar to the one above I'd set a statemachine to start
> counting to 20, send its bits, and then return to state0 where it's waiting
> for your change on lr (IF lr_2d /= lr_3d THEN).
> Regards,
> Pieter Hulshoff


That is a quite interesting way to look for an event, I will defenetly
remember that. The only problem I see it that the clocks are defined
as follows:

input clk --this is fast
counter = counter + 1 -- at clock'event clock='1'

lr <= counter(8);
sclk <= counter(2);
mclk <= counter(0);

and therefore sclk can't really define lr as they are both dependent
on clk.
What I how done for now is to remember what lr was last time, and then
listen for the opposite in a state machine. This has some time-skew
but it works IRL.

Thanks!

/Troels
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