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Re: demux model

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07-03-2003, 08:52 PM

rajan

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Re: demux model

Sorry, I forgot to define 'one' here, which is:
CONSTANT one : unsigned (15 DOWNTO 0) := (0 => '1', OTHERS => '0');

"rajan" <[email protected]> wrote in message
news:CE%[email protected] ...
> Hello colleagues,
>
> I have a demux as below. Is there any other way to write it better in
vhdl.
>
> -- 4to16 demux with shift_left operation --
> wire_sig <= STD_LOGIC_VECTOR (shift_left(one, to_integer(unsigned
> (wire_w))));
>
> regards,
> rajan
>
>

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