FPGA Central

Hi

I have a very simple LFSR in my design that looks as follows:

architecture Behavior of PRNG is
signal temp : std_logic_vector(7 downto 0) := B"01110101";

begin
process(clk)
begin
if ( clk'event and clk='1' ) then
temp <= (temp(1) xor temp(0)) & temp(7 downto 1);
PRNG_OUT <= temp;
end if;
end process;
end architecture Behavior;

The problem that I have here now is obviously that I have the same
seed for each startup of
the simulation! I wonder if there is a very easy way to get 8 random
bits for my temp signal
at the beginning? When checking google the most things I found was
making use of some
random sources from the hardware with oscis and so on but in my case I
just need it for simulation!

Many thanks!

On 17 Feb, 15:31, Martin <[email protected]> wrote:
> Hi
>
> I have a very simple LFSR in my design that looks as follows:
>
> architecture Behavior of PRNG is
> * signal temp : std_logic_vector(7 downto 0) := B"01110101";
>
> * begin
> * process(clk)
> * begin
> * * * * *if ( clk'event and clk='1' ) then
> * * * * * * * * temp * * *<= (temp(1) xor temp(0)) & temp(7 downto 1);
> * * * * * * * * PRNG_OUT *<= temp;
> * * * * * end if;
> * end process;
> end architecture Behavior;
>
> The problem that I have here now is obviously that I have the same
> seed for each startup of
> the simulation! I wonder if there is a very easy way to get 8 random
> bits for my temp signal
> at the beginning? When checking google the most things I found was
> making use of some
> random sources from the hardware with oscis and so on but in my case I
> just need it for simulation!
>
> Many thanks!

Unfortunatly there is no way of getting hold of anything that changes
(like system time) in VHDL. You would have the same problems if you
used the uniform function (generates random reals between 0 and 1)
from the ieee.math_real package too (although this is useful for re-
running input vector sequences).

The only solution I have heard of is to set up a generic in the
testbench as the seed value that is then set via a TCL script when you
run the testbench.

On Feb 17, 10:45*am, Tricky <[email protected]> wrote:
> On 17 Feb, 15:31, Martin <[email protected]> wrote:
>
>
>
> > Hi
>
> > I have a very simple LFSR in my design that looks as follows:
>
> > architecture Behavior of PRNG is
> > * signal temp : std_logic_vector(7 downto 0) := B"01110101";
>
> > * begin
> > * process(clk)
> > * begin
> > * * * * *if ( clk'event and clk='1' ) then
> > * * * * * * * * temp * * *<= (temp(1) xor temp(0)) & temp(7 downto 1);
> > * * * * * * * * PRNG_OUT *<= temp;
> > * * * * * end if;
> > * end process;
> > end architecture Behavior;
>
> > The problem that I have here now is obviously that I have the same
> > seed for each startup of
> > the simulation! I wonder if there is a very easy way to get 8 random
> > bits for my temp signal
> > at the beginning? When checking google the most things I found was
> > making use of some
> > random sources from the hardware with oscis and so on but in my case I
> > just need it for simulation!
>
> > Many thanks!
>
> Unfortunatly there is no way of getting hold of anything that changes
> (like system time) in VHDL. You would have the same problems if you
> used the uniform function (generates random reals between 0 and 1)
> from the ieee.math_real package too (although this is useful for re-
> running input vector sequences).
>
> The only solution I have heard of is to set up a generic in the
> testbench as the seed value that is then set via a TCL script when you
> run the testbench.

How about (if you're running *nix operating system), reading from and
parsing one of the special files (somewhere in dev/* or proc/*) that
might get changed on the fly?

- Kenn

Martin <[email protected]> writes:

> The problem that I have here now is obviously that I have the same
> seed for each startup of the simulation! I wonder if there is a very
> easy way to get 8 random bits for my temp signal at the beginning?

You seem to mix up two issues:

1. You want to change the seed: Valid requirement. Pseudo random
number sequences get kind of boring after a while. Other have
posted solutions. I prefer using generics for that kind of stuff.

2. You want a random seed. Do you really? Think about it. What if you
find a bug and now want to verify your fix. Will you be able to
reproduce the exact system state?

I would use reproducible generated numbers, perhaps the output from
$(date +%s). Store that number along with your simulation data.

Regards
Marcus

--
note that "property" can also be used as syntaxtic sugar to reference
a property, breaking the clean design of verilog; [...]

(seen on http://www.veripool.com/verilog-mode_news.html)

On Tue, 17 Feb 2009 07:56:21 -0800 (PST), [email protected] wrote:

>On Feb 17, 10:45*am, Tricky <[email protected]> wrote:
>> On 17 Feb, 15:31, Martin <[email protected]> wrote:
>
>> > The problem that I have here now is obviously that I have the same
>> > seed for each startup of
>> > the simulation!

>> The only solution I have heard of is to set up a generic in the
>> testbench as the seed value that is then set via a TCL script when you
>> run the testbench.
>
>How about (if you're running *nix operating system), reading from and
>parsing one of the special files (somewhere in dev/* or proc/*) that
>might get changed on the fly?

Or simply read the seed as a number from an ordinary text file.
Echo whatever you want to that file before starting the simulation;
possibly the time in seconds since New Year 1970 (or 1980, depending on OS)

- Brian

Martin wrote:
> Hi
<snip>

> The problem that I have here now is obviously that I have the same
> seed for each startup of
> the simulation! I wonder if there is a very easy way to get 8 random
> bits for my temp signal
> at the beginning? When checking google the most things I found was
> making use of some
> random sources from the hardware with oscis and so on but in my case I
> just need it for simulation!

back in 2001 we had the same requirements for the design of F-CPU,
you'll find the solution in http://f-cpu.seul.org/whygee/pres-is...29_07_2002.tbz
in the f-cpu/vhdl/common directory of the archive.

for clarity, i have put the 2 relevant files at
http://yasep.org/~whygee/random.txt
http://yasep.org/~whygee/random_simple.vhdl
This version gets data from a file,
which is /dev/urandom in this case.
If you want to input from a regular file,
i'll have to search an earlier version
that properly handles wrap-around at
the end of the input file...

> Many thanks!
enjoy and adapt,
yg

--
http://ygdes.com / http://yasep.org

If you are actually going to implement this you can count the phase
difference between a dividend of the board clock (chip oscilator) and an
FPGA generated clock (ring oscilator) of the same approximate frequency, to
generate a random seed.

Dr B

Just a little warning: you'll need 3 taps to get a maximum length 8-
bit sequence.