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Old 11-03-2006, 09:06 AM
ashu
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Default ram not infering as block ram

hi
i had written a code for ram but synthesis tool (SYNPLIFY PRO) is not
infering it as block ram in fact it is
using luts which is consuming lot of chip area.... i m using ALTERA
CYCLONE attribute syn_ramstyle is working well for xilinx device but
not for altera .....could somebody suggest any remedy....code is given
below

thanks
ashwani anand
---------------- --------------- --------------

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_arith.all ;

entity ram is

port (
pclk,sclk,r,w : in std_logic ;
read_a , write_a : in std_logic_vector(11 downto 0 );
data_in : in std_logic_vector(25 downto 0 ) ;
data_out : out std_logic_vector(25 downto 0 )

) ;

end ram ;

architecture a of ram is

type temp is array ( 4095 downto 0 ) of std_logic_vector(25 downto 0) ;

signal t_ram : temp ;

begin


process ( pclk,w ) --------- writing in ram

begin

if ( pclk'event and pclk = '1' ) then

if (w = '1') then

t_ram( conv_integer ( unsigned(write_a ))) <= data_in ;

else


end if ;

end if ;

end process ;


process ( sclk,r ) -----------reading from ram

begin

if ( sclk'event and sclk = '1' ) then

if (r = '1') then

data_out <= t_ram( conv_integer ( unsigned(read_a ))) ;

else

data_out <= (others => '0' ) ;

end if ;

end if ;

end process ;
end a ;

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  #2 (permalink)  
Old 11-06-2006, 01:51 PM
KJ
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Default Re: ram not infering as block ram


ashu wrote:
> hi
> i had written a code for ram but synthesis tool (SYNPLIFY PRO) is not
> infering it as block ram in fact it is
> using luts which is consuming lot of chip area.... i m using ALTERA
> CYCLONE attribute syn_ramstyle is working well for xilinx device but
> not for altera .....could somebody suggest any remedy....code is given
> below

1. Peruse the Altera documentation for the correct method to infer
memory. What you'll find is that what they have there works and
(although they don't mention it) the code you get is portable across
most other FPGA vendors as well without change.
2. Ask yourself why do you required the input 'r' to equal '1' in order
to set data_out (otherwise it is set to 0)? The answer I'm guessing is
that you don't. Data_out could be set as you have it under the "if (r
= '1') then" all the time regardless of whether "r = '1'" or not. This
is the source of your difficulties in getting it to synthesize into
internal memory.
3. General cleanup...i.e. won't fix anything, but makes your code
clearer.
- Both process sensitivity lists should only have 'pclk' in them, they
are not sensitive to either 'w' or 'r'.
- Don't use std_logic_arith. It has problems, it is not a standard;
ieee.numeric_std does not have either of these drawbacks.
- Use "rising_edge(pclk)" instead of "pclk'event and pclk = '1'".
rising_edge() is an ieee.std_logic_1164 function that more clearly
expresses design intent.

By the way, when written correctly you should find that you likely
won't need any 'syn_ramstyle' attribute either. Try it and see,
usually you don't need it.

KJ

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