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-   -   R: pullup on inputs (http://www.fpgacentral.com/group/showthread.php?t=66075)

Max 09-25-2003 11:46 AM

R: pullup on inputs
 
On 25 Sep 2003 02:49:18 -0700
[email protected] (Max) wrote:

> I use xilinx ise webpack 6.1 sp1.
> In may project I tried to add contrains like:
>
> NET "probes<0><0>" LOC = "D11" | PULLUP ;
> NET "probes<0><1>" LOC = "D12" | PULLUP ;
> NET "probes<0><2>" LOC = "C12" | PULLUP ;
>
> This signals are all input.
>
> in place&route report is reported:
> Resolved that IOB <probes<0><0>> must be placed at site D11.
> Resolved that IOB <probes<0><1>> must be placed at site D12.
> Resolved that IOB <probes<0><2>> must be placed at site C12.
>
> and in pad report is not mentioned pullup resistor for that signals.
>
> How can I be sure about the presence of pullup resistors?

In translate report is reported:

Attached a PULLUP primitive to pad net probes<0><2>
Attached a PULLUP primitive to pad net probes<0><1>
Attached a PULLUP primitive to pad net probes<0><0>

but all other reperts doesn't mention this pullups.
So who is right?

thanks


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