FPGA Central

Hi,

I have my VHDL modules which access the processor bus.
I have one more third party core wher in at also uses the processor bus
, now i have no access to their source code.

Now my doubt is how to go about integrating these two since the
tristaing of the processor bus should happen at only one place.

Any innovative soultion?? OR is it really possible or not.

Regards,
Prav

What part are you targetting. Most modern parts no longer support true
*internal* tri-state drivers (and by extension, busses). In these
parts, you will get more mileage by creating an "or" structure, where
the modules output zero's when not selected, and you just OR all the
bus bits together. (ie. bus_0(0) or bus_1(0) or bus_2(0)...) The
downside is that now you can get some serious combinational latencies -
limiting the number of drivers on the bus.

Either way, I would suggest creating two busses - one for writes and
one for reads. The write bus is generally very simple, while the read
bus requires some effort - but the total effort is less than trying to
combine them.