FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > VHDL

VHDL comp.lang.vhdl newsgroup / Usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 09-22-2006, 07:45 PM
Guest
 
Posts: n/a
Default PLEASE I NEED THE VHDL CODE FOR JK FLIPFLOP

I JUST STARTED USING QUARTUS SOFTWARE.I NEED HELP PLEASE

Reply With Quote
  #2 (permalink)  
Old 09-24-2006, 01:29 AM
rickman
Guest
 
Posts: n/a
Default Re: PLEASE I NEED THE VHDL CODE FOR JK FLIPFLOP

[email protected] wrote:
> I JUST STARTED USING QUARTUS SOFTWARE.I NEED HELP PLEASE


Assuming that you know how to write a clocked process, a JK FF should
be a simple matter of coding the truth table for a JK FF. Lets see if
I can remember how that goes.

J K | Q+1
---------
0 0 | Q
0 1 | 0
1 0 | 1
1 1 | ~Q


So the VHDL inside the process could look like...

case JK is
when "00" => Q <= Q;
when "01" => Q <= '0';
when "10" => Q <= '1';
when "11" => Q <= not Q;
others => Q <= 'X';
end case;

You should be able to put the process and signal definitions around
this.

Reply With Quote
  #3 (permalink)  
Old 09-24-2006, 08:31 PM
rickman
Guest
 
Posts: n/a
Default Re: PLEASE I NEED THE VHDL CODE FOR JK FLIPFLOP

rickman wrote:
> [email protected] wrote:
> > I JUST STARTED USING QUARTUS SOFTWARE.I NEED HELP PLEASE

>
> Assuming that you know how to write a clocked process, a JK FF should
> be a simple matter of coding the truth table for a JK FF. Lets see if
> I can remember how that goes.
>
> J K | Q+1
> ---------
> 0 0 | Q
> 0 1 | 0
> 1 0 | 1
> 1 1 | ~Q
>
>
> So the VHDL inside the process could look like...
>
> case JK is
> when "00" => Q <= Q;
> when "01" => Q <= '0';
> when "10" => Q <= '1';
> when "11" => Q <= not Q;
> others => Q <= 'X';
> end case;
>
> You should be able to put the process and signal definitions around
> this.


I figured this was some kid asking for help with his homework. I
didn't realize that he is actually asking for someone to do the entire
assignment for him. I thought I could help by getting him started on
the core in case he was stuck on a way to do this. But then I get an
email asking for the entire assignment!

--------------------
From: "coldplay112" <[email protected]>
To: "rickman" <[email protected]>
Subject: THE VHDL CODE FOR JK FLIPFLOP


PLEASE SIR GIVE THE WHOLE CODE SIR,FROM THE ENTITY JK FLIPFLOP TO END
BEHAVIOR.I AM A NOVICE IN THIS COURSE.
------------------

Maybe I am in the wrong business. I could charge $25 each for doing 10
minute homework assignments and rake in some real dough, especially if
I do it for everyone in the same class!!!

I guess it is a bit like spamming. You only need one guy in a thousand
who replies to make it worth your while...

Reply With Quote
  #4 (permalink)  
Old 09-25-2006, 04:00 PM
coldplay112
Guest
 
Posts: n/a
Default I HAVE FIGURED IT OUT THE VHDL CODE FOR JK FLIPFLOP

IT WORK WITH MY QUARTUS ALTERA VDHL PROGRAM.THANKS FOR PUTTING PRESSURE
ON ME.I WILL STRIVE TO GET AN A IN THIS COURSE GRADUALLY,I HAVE A TEST
BYE.

Reply With Quote
  #5 (permalink)  
Old 09-25-2006, 07:47 PM
Isaac Bosompem
Guest
 
Posts: n/a
Default Re: PLEASE I NEED THE VHDL CODE FOR JK FLIPFLOP


rickman wrote:
> rickman wrote:
> > [email protected] wrote:
> > > I JUST STARTED USING QUARTUS SOFTWARE.I NEED HELP PLEASE

> >
> > Assuming that you know how to write a clocked process, a JK FF should
> > be a simple matter of coding the truth table for a JK FF. Lets see if
> > I can remember how that goes.
> >
> > J K | Q+1
> > ---------
> > 0 0 | Q
> > 0 1 | 0
> > 1 0 | 1
> > 1 1 | ~Q
> >
> >
> > So the VHDL inside the process could look like...
> >
> > case JK is
> > when "00" => Q <= Q;
> > when "01" => Q <= '0';
> > when "10" => Q <= '1';
> > when "11" => Q <= not Q;
> > others => Q <= 'X';
> > end case;
> >
> > You should be able to put the process and signal definitions around
> > this.

>
> I figured this was some kid asking for help with his homework. I
> didn't realize that he is actually asking for someone to do the entire
> assignment for him. I thought I could help by getting him started on
> the core in case he was stuck on a way to do this. But then I get an
> email asking for the entire assignment!
>
> --------------------
> From: "coldplay112" <[email protected]>
> To: "rickman" <[email protected]>
> Subject: THE VHDL CODE FOR JK FLIPFLOP
>
>
> PLEASE SIR GIVE THE WHOLE CODE SIR,FROM THE ENTITY JK FLIPFLOP TO END
> BEHAVIOR.I AM A NOVICE IN THIS COURSE.
> ------------------
>
> Maybe I am in the wrong business. I could charge $25 each for doing 10
> minute homework assignments and rake in some real dough, especially if
> I do it for everyone in the same class!!!
>
> I guess it is a bit like spamming. You only need one guy in a thousand
> who replies to make it worth your while...


Hahaha,

The way you guys respond to thse people is hilarious.

-Isaac

Reply With Quote
  #6 (permalink)  
Old 09-25-2006, 10:10 PM
fabbl
Guest
 
Posts: n/a
Default Re: I HAVE FIGURED IT OUT THE VHDL CODE FOR JK FLIPFLOP

Try reading a book.

> IT WORK WITH MY QUARTUS ALTERA VDHL PROGRAM.THANKS FOR PUTTING PRESSURE
> ON ME.I WILL STRIVE TO GET AN A IN THIS COURSE GRADUALLY,I HAVE A TEST
> BYE.
>
>



Reply With Quote
  #7 (permalink)  
Old 09-26-2006, 08:54 PM
Guest
 
Posts: n/a
Default Re: PLEASE I NEED THE VHDL CODE FOR JK FLIPFLOP

rickman wrote:
> I figured this was some kid asking for help with his homework. I
> didn't realize that he is actually asking for someone to do the entire
> assignment for him. I thought I could help by getting him started on
> the core in case he was stuck on a way to do this. But then I get an
> email asking for the entire assignment!
>
> --------------------
> From: "coldplay112" <[email protected]juno.com>
> To: "rickman" <[email protected]>
> Subject: THE VHDL CODE FOR JK FLIPFLOP
>
>
> PLEASE SIR GIVE THE WHOLE CODE SIR,FROM THE ENTITY JK FLIPFLOP TO END
> BEHAVIOR.I AM A NOVICE IN THIS COURSE.
> ------------------
>
> Maybe I am in the wrong business. I could charge $25 each for doing 10
> minute homework assignments and rake in some real dough, especially if
> I do it for everyone in the same class!!!
>
> I guess it is a bit like spamming. You only need one guy in a thousand
> who replies to make it worth your while...




Is it only me or are the kids really getting dumber by the day?
Not to mention cocky. nowadays, they are DEMANDING and REQUIERING
answers.


-burns

Reply With Quote
  #8 (permalink)  
Old 09-26-2006, 08:57 PM
Guest
 
Posts: n/a
Default Re: PLEASE I NEED THE VHDL CODE FOR JK FLIPFLOP

rickman wrote:
> I figured this was some kid asking for help with his homework. I
> didn't realize that he is actually asking for someone to do the entire
> assignment for him. I thought I could help by getting him started on
> the core in case he was stuck on a way to do this. But then I get an
> email asking for the entire assignment!
>
> --------------------
> From: "coldplay112" <[email protected]>
> To: "rickman" <[email protected]>
> Subject: THE VHDL CODE FOR JK FLIPFLOP
>
>
> PLEASE SIR GIVE THE WHOLE CODE SIR,FROM THE ENTITY JK FLIPFLOP TO END
> BEHAVIOR.I AM A NOVICE IN THIS COURSE.
> ------------------
>
> Maybe I am in the wrong business. I could charge $25 each for doing 10
> minute homework assignments and rake in some real dough, especially if
> I do it for everyone in the same class!!!
>
> I guess it is a bit like spamming. You only need one guy in a thousand
> who replies to make it worth your while...




Is it only me or are the kids really getting dumber by the day?
Not to mention cocky. nowadays, they are DEMANDING and REQUIERING
answers.


-burns

Reply With Quote
  #9 (permalink)  
Old 09-27-2006, 02:46 AM
james
Guest
 
Posts: n/a
Default Re: PLEASE I NEED THE VHDL CODE FOR JK FLIPFLOP

On 26 Sep 2006 12:54:21 -0700, [email protected] wrote:

>+++Is it only me or are the kids really getting dumber by the day?
>+++Not to mention cocky. nowadays, they are DEMANDING and REQUIERING
>+++answers.
>+++
>+++
>+++-burns

***********

Just lazy.

james
Reply With Quote
  #10 (permalink)  
Old 09-27-2006, 08:41 AM
Michael Jørgensen
Guest
 
Posts: n/a
Default Re: I HAVE FIGURED IT OUT THE VHDL CODE FOR JK FLIPFLOP


"fabbl" <[email protected]> wrote in message
news:[email protected] om...
> Try reading a book.
>
> > IT WORK WITH MY QUARTUS ALTERA VDHL PROGRAM.THANKS FOR PUTTING PRESSURE
> > ON ME.I WILL STRIVE TO GET AN A IN THIS COURSE GRADUALLY,I HAVE A TEST
> > BYE.


Start by switch off "caps lock".

-Michael.


Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Infer RS FlipFlop Scott Gravenhorst Verilog 6 12-10-2008 08:56 PM
FlipFlop testbench with reset Verictor Verilog 2 03-06-2007 05:49 PM
generating VHDL code from Matlab code for DSP - wavelet image compression EEngineer FPGA 8 02-13-2007 03:22 PM
sequential circuits(T-flipflop) in modelsim G.K. RAMAM Verilog 2 09-13-2004 06:31 AM
asynchronous flipflop in PLD? Blackie Beard Verilog 4 07-09-2004 05:07 AM


All times are GMT +1. The time now is 06:13 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved