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Old 10-31-2003, 03:19 PM
Yttrium
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Default a newbie question about modelsim and testbenches

well, this is my first big VHDL/FPGA project (i already done some small
one's) and i was just wondering if the ModelSim Simulator gives me a

"# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the
result will be 'X'(es).
# Time: 5875 ns Iteration: 2 Instance: /testbench/uut"

warning should i really pay attention to it or not? because when i look at
the signals there's nothing wrong with what they're doing and the module's
simulation is perfect! usually i try to solve as many warning as possible
but i get this one from time to time and never pay attention to this one!

thanx for replying,

greetings,

Yttrium


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Old 10-31-2003, 03:41 PM
Jonathan Bromley
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Default Re: a newbie question about modelsim and testbenches

"Yttrium" <[email protected]> wrote in message
news:[email protected]

> "# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic
> operand, the result will be 'X'(es).
> # Time: 5875 ns Iteration: 2 Instance: /testbench/uut"
>
> warning should i really pay attention to it or not? because when i look at
> the signals there's nothing wrong with what they're doing and the module's
> simulation is perfect! usually i try to solve as many warning as possible
> but i get this one from time to time and never pay attention to this one!


It is common to get this error in VHDL designs at start-up
(time 0 ns) before the system is reset. In this case, the
error is usually harmless.

If it occurs at any later time in simulation, as your error
seems to indicate, it is more likely to be serious. You
should track down exactly where it comes from, and check
for yourself that it reflects normal and harmless behaviour
of some uninitialised register.

Consider this:
signal value: unsigned(7 downto 0);
...
if value = 0 then ....

Now, if "value" contains X in simulation, the comparison will be
false and nothing will happen. But in the real hardware, the
uninitialised "value" MIGHT contain zero by chance - and then
the condition would be true, and something different would
happen. Are you happy to ignore that kind of issue ????

If you really want to get rid of these warnings, you can do it
in ModelSim. Look at menu item Simulate/Simulation_Options;
under the Defaults tab you will find a check box
"Suppress warnings from IEEE Numeric Std packages".
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: [email protected]
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.



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