FPGA Central

Hi All,

1.Added a new User Delay and Constraint Editor panel. You can add,
delete, or update User Delays or Constraints.
2 .These User Delays and User Constraints are saved at the top of
the .tim file.
3.Changing a User Delay or User Constraint updates every one of the
same type in the diagram.
4.Files created with previous versions are converted to this new
format when saved.
5.Added Python Interpreter, Jython 2.5. Now you can write scripts
in Python.
6.Execute Python scripts using the same script dialog for the
beanshell scripts or from Jython command line window.
7.Included start_app.py script in the install directory that will
start the TimingAnalyzer from a Jython command line window.
8.Updated spice_pwl.bsh. This beanshell script generates spice
piece wise linear test vectors for DigitalBus.
9.Included dff.py. This Python script shows how to generate a
timing diagram for a D Flip Flop.

Anyone interested in helping convert the Java scripts (in the scripts
dir) to Python should let me know.
Dan Fabrizio

www.timing-diagrams.com