"Quinnie" wrote:
> I need VHDL code for Modified Booth's multiplier
Signed / Unsigned? Both? ;-)
The Booth-Encoder ist is combinational logic. If you understand the
mathematical principle, it is very easy to implement.
The generation of the partial products (PPG) depends on whether signed /
unsigned multipication or both is needed. There are some tricks for sign
extension, too.
The partial product reduction (PPR) is "free" to implement. CSA and
Wallace-Tree are the most common.
The final Carry-Propagate-Adder (CPA) is also "free". CLA is the most
common.
> and Add/Shift
> multiplier. They have to be structural design (not behavorial)...Any
> help would be greatly appreciated. Thnx!
Uhmm .. this is a VHDL-newsgroup, not a market for IP cores. ;-)
I recommended the following links:
Booth encoded array multipliers:
http://arith.cs.ucla.edu/dissertatio...on_huang03.pdf
fast CPA:
http://twins.ee.nctu.edu.tw/~chsung/...tation_ts2.pdf
Ralf