FPGA Central

Hello everyone? I'm June from Korea.
I was doing a homework, where I encountered a trouble.
I'll appreciate if you can help me.

The Problem is: I checked the grammar again and again, but found no
errors.
Still, ISE says " More actuals found than formals in port map"
There's no information about this error message in Google.
Please! tell me what's the problem and how to solve it.

-June-

architecture-----------------------------------------------------------------------------------------
stage5 : fourbitadder port map (x(3),x(2),x(1),x(0),
y(3),y(2),y(1),y(0), c, sum(3),sum(2),sum(1),sum(0), carry);

*Error message occurs here** More actuals found than formals in port
map***
-----------------------------------------------------------------------------------------------------------

fourbitadder is refered as follows:

architecture----------------------------------------------------------------------------------------
component fourbitadder
port ( a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
cin : in std_logic;
s : out std_logic_vector(3 downto 0);
cout : out std_logic);
end component;
----------------------------------------------------------------------------------------------------------

june wrote:
> Hello everyone? I'm June from Korea.
> I was doing a homework, where I encountered a trouble.
> I'll appreciate if you can help me.
>
> The Problem is: I checked the grammar again and again, but found no
> errors.
> Still, ISE says " More actuals found than formals in port map"
> There's no information about this error message in Google.
> Please! tell me what's the problem and how to solve it.
>
> -June-
>
> architecture-----------------------------------------------------------------------------------------
> stage5 : fourbitadder port map (x(3),x(2),x(1),x(0),
> y(3),y(2),y(1),y(0), c, sum(3),sum(2),sum(1),sum(0), carry);
>
> *Error message occurs here** More actuals found than formals in port
> map***
> -----------------------------------------------------------------------------------------------------------
>
> fourbitadder is refered as follows:
>
> architecture----------------------------------------------------------------------------------------
> component fourbitadder
> port ( a : in std_logic_vector(3 downto 0);
> b : in std_logic_vector(3 downto 0);
> cin : in std_logic;
> s : out std_logic_vector(3 downto 0);
> cout : out std_logic);
> end component;
> ----------------------------------------------------------------------------------------------------------
>
I suspect (without actually running it) that the issue is that your
formals & actuals are of different types. Each formal & actual counts 1,
regardless of its size/type. So you have 14 actuals, & 5 formals. The
fact that they total the same number of bits doesn't help.
How about this:
signal x, y, sum : std_logic_vector(3 downto 0);
signal c, carry : std_logic;
stage5 : fourbitadder port map (x, y, c, sum, carry);

If you really want your signals broken up into bits (to attach to
top-level pins?), you do that explicitly at the top level.

"june" <[email protected]> wrote in message
news:[email protected] ps.com...
> Hello everyone? I'm June from Korea.
> I was doing a homework, where I encountered a trouble.
> I'll appreciate if you can help me.
>
> The Problem is: I checked the grammar again and again, but found no
> errors.
> Still, ISE says " More actuals found than formals in port map"
> There's no information about this error message in Google.
> Please! tell me what's the problem and how to solve it.
>
> -June-
>
> architecture-----------------------------------------------------------------------------------------
> stage5 : fourbitadder port map (x(3),x(2),x(1),x(0),
> y(3),y(2),y(1),y(0), c, sum(3),sum(2),sum(1),sum(0), carry);
>
> *Error message occurs here** More actuals found than formals in port
> map***
> -----------------------------------------------------------------------------------------------------------
>
> fourbitadder is refered as follows:
>
> architecture----------------------------------------------------------------------------------------
> component fourbitadder
> port ( a : in std_logic_vector(3 downto 0);
> b : in std_logic_vector(3 downto 0);
> cin : in std_logic;
> s : out std_logic_vector(3 downto 0);
> cout : out std_logic);
> end component;
> ----------------------------------------------------------------------------------------------------------
>
There are only 5 ports expected (a, b, cin, s and cout) but you've supplied
14 arguments. The number that are expected (the formals) come from your
component definition, the actuals are the list of 14 signals that you
provided. Here are a couple different ways to correct:

--- 1. Using the '&' operator to concatenate the individual signals
stage5 : fourbitadder port map (x(3) & x(2) & x(1) & x(0),
y(3) & y(2) & y(1) & y(0), c, sum(3) & sum(2) & sum(1) & sum(0), carry);

-- 2. Simply use the correct vectors
stage5 : fourbitadder port map (x(3 downto 0),
y(3 downto 0), c, sum(3 downto 0), carry);

-- 3. Use explicit port mappings (this is better practice than relying on
the position in the mapping as you've done

stage5 : fourbitadder port map (
a => x(3 downto 0),
b => y(3 downto 0),
cin => c,
s => sum(3 downto 0),
cout => carry);

KJ