FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > VHDL

VHDL comp.lang.vhdl newsgroup / Usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 10-07-2003, 07:52 PM
Niv
Guest
 
Posts: n/a
Default ModelSim & tcl testbench

I'm reasonably OK at writing VHDL code & testbenches, but I now need to
write a testbench in tcl rather than VHDL
so I can control the flow better. (I have a counter that wraps at 5
seconds, so i want to use FORCE to make it jump from a low to a high value,
by using the WHEN command in tcl.
(There's also a large counter that wraps every 550 years! Dont ask, it's
what the softies require, but even they can't explain).

However, I don't really know where to start although I have done some simple
tcl programming & scripting.

1. Do I just read in the VHDL design entity into ModelSim
2. Anyone have a sample/simple bit of code.
3. Point me a t the right website "tcl & modelsim for idiots" etc.

Regards, Niv.

--
remove ***SPAM-OFF** to reply


Reply With Quote
  #2 (permalink)  
Old 10-07-2003, 08:57 PM
Jonathan Bromley
Guest
 
Posts: n/a
Default Re: ModelSim & tcl testbench

"Niv" <niv**mines_a_pint_you_spamheads**@ntlworld.com> wrote in
message news:[email protected]

> I'm reasonably OK at writing VHDL code & testbenches, but I now
> need to write a testbench in tcl rather than VHDL so I can
> control the flow better.


VHDL can do control stuff pretty well, too... are you *sure* you need
a Tcl testbench?

> Dont ask, it's what the softies require, but even they can't explain


hmmm... I sympathise.

> 1. Do I just read in the VHDL design entity into ModelSim


You *can* do that, but you are likely to end up with a very inefficient
(slow) simulation because you need interaction between Tcl and the
simulator for each and every input signal transition. It's likely
to be far better to write the detailed time-dependent signal-wiggling
stuff in a VHDL test harness, and provide a few signals to control its
functionality. You can then manipulate those "control knobs" from
your Tcl jacket using [force] commands.

> 2. Anyone have a sample/simple bit of code.


Sure. Fancy coming on one of our Tcl courses? :-)

You need to learn just three new ModelSim commands: [force], [when]
and [examine]. Read the docs on them, in detail. Note that you can
[force] signal changes planned for the future, and [examine] signal
values in the past; that means you don't need to stop and start the
sim very frequently, but instead you can run it in "batch mode",
setting-up numerous planned signal changes and then examining all
their effects when you eventually stop the sim.

> 3. Point me at the right website "tcl & modelsim for idiots" etc.


Not too many idiots visit our website, but you may still find a few
hints and code snippets at
www.doulos.com/knowhow/tcltk

We also have some nifty tricks for interaction between a running VHDL
sim and a Tcl program using pipes, but that is MUCH too interesting
to give away on the NG...

When you get really good at this stuff you will find yourself
controlling ModelSim from Tcl via a sockets interface. Ask your
friendly local Mentor rep about this, because the standard docs
don't say too much about it.

Enjoy.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: [email protected]
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.



Reply With Quote
  #3 (permalink)  
Old 10-07-2003, 10:26 PM
Mike Treseler
Guest
 
Posts: n/a
Default Re: ModelSim & tcl testbench

Niv wrote:
> I'm reasonably OK at writing VHDL code & testbenches, but I now need to
> write a testbench in tcl rather than VHDL


> (There's also a large counter that wraps every 550 years!


Consider passing the counter reset value to the entity
as a generic constant.

Make the default is all zero, so synthesis is not affected.

The VHLD testbench can then drive multiple instances
with different generic reset values,
say zero and 549.99999 years.

-- Mike Treseler

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
problems with using altera vhdl testbench in ModelSim [email protected] FPGA 3 11-08-2006 02:57 AM
Problem with Verilog testbench in ModelSim czeczek Verilog 2 09-28-2006 08:15 PM
Testbench using Modelsim/VHDL - simple signal generation problem fast[email protected] FPGA 11 10-01-2005 01:41 PM
Internal Signals and other questions with ModelSim XE/II Starter 5.7g VHDL Testbench Martin Maurer FPGA 2 05-21-2004 05:45 AM


All times are GMT +1. The time now is 02:18 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved