On 12 Mar 2007 06:48:19 -0700, "fpgaengineer"
<
[email protected]> wrote:
>Im am trying to simulate a full design (top entity of a Xilinx
>Project) and stumble of a modelsim error:
>
>Netgen produces the full *.vhd and compiling it from ModelSim ended
>with no error. But after starting the simulation, the following error
>occurs: "Fatal error in Process determine_phase_shift at 7814"
>
>In the Unisim.Lib (which is correctly referenced in the full vhdl) I
>am observing the attched lines, where in 7814 it says " ps_step_int :=
>(PS_STEP / 1 ps ) * 1; "
My best guess is that you are running ModelSim with a default
time resolution greater than 1ps, so your 1ps time divisor is
being rounded to zero and you're therefore getting a
divide-by-zero error. When invoking ModelSim, try using
"-t ps" on the "vsim" command line.
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