FPGA Central

Hello,

I'm facing a problem while using the MOD operator in VHDL.

The error is the following:
"Error (10327): VHDL error at deblocking_filter.vhd(627): can't
determine definition of operator ""mod"" -- found 0 possible
definitions"

I'm using the following libraries:
LIBRARY ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;

Thanks a lot for any information.
Guilherme Corrêa.

Guilherme Corrêa wrote:
> Hello,
>
> I'm facing a problem while using the MOD operator in VHDL.
>
> The error is the following:
> "Error (10327): VHDL error at deblocking_filter.vhd(627): can't
> determine definition of operator ""mod"" -- found 0 possible
> definitions"
>
> I'm using the following libraries:
> LIBRARY ieee;
> USE IEEE.std_logic_1164.all;
> USE IEEE.std_logic_arith.all;
> USE IEEE.std_logic_unsigned.all;
> USE IEEE.numeric_std.all;
>
> Thanks a lot for any information.
> Guilherme Corrêa.

Wow that's a lot of packages...

You definitely don't want numeric_std *and* std_logic_arith as they have
duplicate definitions.

The first step is to remove the packages you don't need. That may fix
the problem.

If that doesn't work, post the offending piece of code,

regards
Alan

--
Alan Fitch
Doulos
http://www.doulos.com

On 12 jan, 13:01, Alan Fitch <[email protected]> wrote:
> Guilherme Corrêa wrote:
> > Hello,
>
> > I'm facing a problem while using the MOD operator in VHDL.
>
> > The error is the following:
> > "Error (10327): VHDL error at deblocking_filter.vhd(627): can't
> > determine definition of operator ""mod"" -- found 0 possible
> > definitions"
>
> > I'm using the following libraries:
> > LIBRARY ieee;
> > USE IEEE.std_logic_1164.all;
> > USE IEEE.std_logic_arith.all;
> > USE IEEE.std_logic_unsigned.all;
> > USE IEEE.numeric_std.all;
>
> > Thanks a lot for any information.
> > Guilherme Corrêa.
>
> Wow that's a lot of packages...
>
> You definitely don't want numeric_std *and* std_logic_arith as they have
> duplicate definitions.
>
> The first step is to remove the packages you don't need. That may fix
> the problem.
>
> If that doesn't work, post the offending piece of code,
>
> regards
> Alan
>
> --
> Alan Fitch
> Douloshttp://www.doulos.com

Firstly I had just these two packages:
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;

The error was the same ("Error (10327): can't determine definition of
operator ""mod"" -- found 0 possible definitions").

Then I read somewhere that I should use IEEE.std_logic_arith.all also.
I did it and the error was still there ("Error (10327): can't
determine definition of operator ""mod"" -- found 0 possible
definitions").

Guilherme.

Guilherme Corrêa wrote:
> On 12 jan, 13:01, Alan Fitch <[email protected]> wrote:
>> Guilherme Corrêa wrote:
>>> Hello,
>>> I'm facing a problem while using the MOD operator in VHDL.
>>> The error is the following:
>>> "Error (10327): VHDL error at deblocking_filter.vhd(627): can't
>>> determine definition of operator ""mod"" -- found 0 possible
>>> definitions"
>>> I'm using the following libraries:
>>> LIBRARY ieee;
>>> USE IEEE.std_logic_1164.all;
>>> USE IEEE.std_logic_arith.all;
>>> USE IEEE.std_logic_unsigned.all;
>>> USE IEEE.numeric_std.all;
>>> Thanks a lot for any information.
>>> Guilherme Corrêa.
>> Wow that's a lot of packages...
>>
>> You definitely don't want numeric_std *and* std_logic_arith as they have
>> duplicate definitions.
>>
>> The first step is to remove the packages you don't need. That may fix
>> the problem.
>>
>> If that doesn't work, post the offending piece of code,
>>
>> regards
>> Alan
>>
>> --
>> Alan Fitch
>> Douloshttp://www.doulos.com
>
> Firstly I had just these two packages:
> USE IEEE.std_logic_1164.all;
> USE IEEE.std_logic_unsigned.all;
>
> The error was the same ("Error (10327): can't determine definition of
> operator ""mod"" -- found 0 possible definitions").
>
> Then I read somewhere that I should use IEEE.std_logic_arith.all also.
> I did it and the error was still there ("Error (10327): can't
> determine definition of operator ""mod"" -- found 0 possible
> definitions").
>
> Guilherme.

In that case can you post the code at line 627, and also tell me the
data types being used with the mod operator?

regards
Alan

--
Alan Fitch
Doulos
http://www.doulos.com

On 12 jan, 13:53, Alan Fitch <[email protected]> wrote:
> Guilherme Corrêa wrote:
> > On 12 jan, 13:01, Alan Fitch <[email protected]> wrote:
> >> Guilherme Corrêa wrote:
> >>> Hello,
> >>> I'm facing a problem while using the MOD operator in VHDL.
> >>> The error is the following:
> >>> "Error (10327): VHDL error at deblocking_filter.vhd(627): can't
> >>> determine definition of operator ""mod"" -- found 0 possible
> >>> definitions"
> >>> I'm using the following libraries:
> >>> LIBRARY ieee;
> >>> USE IEEE.std_logic_1164.all;
> >>> USE IEEE.std_logic_arith.all;
> >>> USE IEEE.std_logic_unsigned.all;
> >>> USE IEEE.numeric_std.all;
> >>> Thanks a lot for any information.
> >>> Guilherme Corrêa.
> >> Wow that's a lot of packages...
>
> >> You definitely don't want numeric_std *and* std_logic_arith as they have
> >> duplicate definitions.
>
> >> The first step is to remove the packages you don't need. That may fix
> >> the problem.
>
> >> If that doesn't work, post the offending piece of code,
>
> >> regards
> >> Alan
>
> >> --
> >> Alan Fitch
> >> Douloshttp://www.doulos.com
>
> > Firstly I had just these two packages:
> > USE IEEE.std_logic_1164.all;
> > USE IEEE.std_logic_unsigned.all;
>
> > The error was the same ("Error (10327): can't determine definition of
> > operator ""mod"" -- found 0 possible definitions").
>
> > Then I read somewhere that I should use IEEE.std_logic_arith.all also.
> > I did it and the error was still there ("Error (10327): can't
> > determine definition of operator ""mod"" -- found 0 possible
> > definitions").
>
> > Guilherme.
>
> In that case can you post the code at line 627, and also tell me the
> data types being used with the mod operator?
>
> regards
> Alan
>
> --
> Alan Fitch
> Douloshttp://www.doulos.com

line 627 is here:
write_line_T1 <= (count_cycle - "000001") MOD "000100";

but I have also tried this:
write_line_T1 <= 15 MOD 2;
and the same error occur.

types:
write_line: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL count_cycle: STD_LOGIC_VECTOR(5 DOWNTO 0);

Thanks again.
Guilherme.

<snip>

> line 627 is here:
> write_line_T1 <= (count_cycle - "000001") MOD "000100";
>
> but I have also tried this:
> write_line_T1 <= 15 MOD 2;
> and the same error occur.
>
> types:
> write_line: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
> SIGNAL count_cycle: STD_LOGIC_VECTOR(5 DOWNTO 0);
>
> Thanks again.
> Guilherme.

OK, as you've discovered there's no mod for std_logic_vector.
One way to do it is to use numeric_std as follows:

use IEEE.Numeric_std.all;

Then change line 627 as follows:

write_line_T1 <= std_logic_vector( (unsigned(count_cycle) -1) mod 4);

(I assume you meant "mod 4" not "mod 2" as you had "000100" in your
original code)

Numeric_std defines unsigned arithmetic operators on combinations of
unsigned / natural and unsigned/unsigned, each operator producing an
unsigned result.

I am assuming you want unsigned arithmetic.

regards
Alan

P.S. If you end up requiring a lot of arithmetic operations, then it
would make sense to declare some of your signals unsigned instead of
std_logic_vector, as that avoids a lot of type conversions. However if
this is the only line that requires arithmetic, there's no problem doing
type conversion as you need it.

--
Alan Fitch
Doulos
http://www.doulos.com

On 12 jan, 14:13, Alan Fitch <[email protected]> wrote:
> <snip>
>
> > line 627 is here:
> > write_line_T1 <= (count_cycle - "000001") MOD "000100";
>
> > but I have also tried this:
> > write_line_T1 <= 15 MOD 2;
> > and the same error occur.
>
> > types:
> > write_line: * * * *IN STD_LOGIC_VECTOR (1 DOWNTO 0);
> > SIGNAL count_cycle: STD_LOGIC_VECTOR(5 DOWNTO 0);
>
> > Thanks again.
> > Guilherme.
>
> OK, as you've discovered there's no mod for std_logic_vector.
> One way to do it is to use numeric_std as follows:
>
> use IEEE.Numeric_std.all;
>
> Then change line 627 as follows:
>
> write_line_T1 <= std_logic_vector( (unsigned(count_cycle) -1) mod 4);
>
> (I assume you meant "mod 4" not "mod 2" as you had "000100" in your
> original code)
>
> Numeric_std defines unsigned arithmetic operators on combinations of
> unsigned / natural and unsigned/unsigned, each operator producing an
> unsigned result.
>
> I am assuming you want unsigned arithmetic.
>
> regards
> Alan
>
> P.S. If you end up requiring a lot of arithmetic operations, then it
> would make sense to declare some of your signals unsigned instead of
> std_logic_vector, as that avoids a lot of type conversions. However if
> this is the only line that requires arithmetic, there's no problem doing
> type conversion as you need it.
>
> --
> Alan Fitch
> Douloshttp://www.doulos.com

It worked! Thanks a lot.

Best regards,
Guilherme Corrêa.

On Jan 12, 8:13*am, Alan Fitch <[email protected]> wrote:
> P.S. If you end up requiring a lot of arithmetic operations, then it
> would make sense to declare some of your signals unsigned instead of
> std_logic_vector, as that avoids a lot of type conversions. However if
> this is the only line that requires arithmetic, there's no problem doing
> type conversion as you need it.

Rather than only using unsigned when you need to do arithmetic, I
would think about how the contents of an SLV are interpreted. If they
are interpreted numerically, then use unsigned or signed types as
appropriate. If they are interpreted as a collection of bits, without
a consistent numerical interpretation, then use SLV. For instance, an
address bus would be a good place to use unsigned types. A data bus
might need to be SLV because at different times it may contain signed,
unsigned, or non-numeric quantities. But you can do pretty much
anything with unsigned or signed that you can with SLV.

The only place to be careful about non-SL or non-SLV types is at the
top level entity of your design. The reason is that the post-synthesis
(and/or post-P&R) VHDL will almost certainly use SL & SLV, so using
them in your RTL makes it easier to swap RTL for post-synthesis code
in your testbench.

Andy