FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > VHDL

VHDL comp.lang.vhdl newsgroup / Usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 09-22-2006, 04:37 AM
jtw
Guest
 
Posts: n/a
Default Missing direction on entity port

As a result of changing what was a generic to an input port, I omitted the
keyword 'in'. Neither the simulator (Modelsim 6.x) nor the synthesis tool
(Synplicity 8.4) challenged me on this. Is there a specified default? Or
is this a tool thing? (In case it isn't obvious, both the simulation and the
synthesis turned out okay.)

Jason


Reply With Quote
  #2 (permalink)  
Old 09-22-2006, 09:26 PM
Paul Uiterlinden
Guest
 
Posts: n/a
Default Re: Missing direction on entity port

jtw wrote:

> As a result of changing what was a generic to an input port, I
> omitted the
> keyword 'in'. Neither the simulator (Modelsim 6.x) nor the
> synthesis tool
> (Synplicity 8.4) challenged me on this. Is there a specified
> default? Or is this a tool thing? (In case it isn't obvious, both
> the simulation and the synthesis turned out okay.)


The mode is optional with IN as default. The same goes for the formal
parameters in the parameter list declaration of subprograms
(procedures and functions). So it is perfectly OK that the simulator
and synthesizer do not complain.

--
Paul.

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Support for mixed-direction port concatenations? Evan Lavelle Verilog 4 06-07-2007 11:18 PM
Bus direction john VHDL 9 10-17-2005 04:11 PM
Determine entity/component port signal range Sven Heithecker VHDL 2 08-02-2004 07:53 PM
INOUT port on entity minkowsky VHDL 29 02-28-2004 12:58 PM


All times are GMT +1. The time now is 10:23 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved