FPGA Central

HI, all
I've encounter to write a multiplexer many times , for example, a
four-bit mux:

library ieee;
use ieee.std_logic_1164.all;

entity mux4 is
port (X,Y : in std_ulogic_vector(3 downto 0);
Sel : in std_ulogic;
Z : out std_ulogic_vector(3 downto 0));
end entity;

and I found out there would be two method to implement it:
ONE:
Z <= X when Sel = '0' else Y;

THE OTHER:
Z <= X when Sel = '0' else
Y when Sel = '1' else
(others => '-');

I know that if the signal's type is 'bit'/'bit_vector" , there would
not be much to discuss, but now the
signal is a multiple value logic....
Are those two method equivalent ? which one is better? I mean which
one would require less
resource or/and operate fast when it 's synthesized? Is there any
method other than those
two more better?

Thanks
//Fano