FPGA Central

Hi all,

I have created a component with unconstrained std_logic_vector type input
and output. Can I make it work with std_logic as well? The component is
basically a pipeline of 2 FFs.

Thanks,
/Mikhail

On Tue, 27 Jul 2004 11:01:03 -0400,
"MM" <[email protected]> wrote:

>I have created a component with unconstrained std_logic_vector type input
>and output. Can I make it work with std_logic as well? The component is
>basically a pipeline of 2 FFs.

No, but you can easily make it work with a single-element vector
port such as std_logic_vector(0 downto 0). You could then create
a one-element vector signal to connect to each port, and copy it
to/from your scalar signal:

signal vec_in, vec_out: std_logic_vector(0 downto 0);
signal scalar_in, scalar_out: std_logic;
...
instance : Pipeline_component
port map (input => vec_in, output => vec_out);

vec_in(0) <= scalar_in;
scalar_out <= vec_out(0);

Alternatively, and probably better, you can simply
connect up your scalar to one single numbered bit of the
port, thereby establishing the vector range for the port
as well as making the connection:

instance : Pipeline_component
port map (input(0) => scalar_in, output(0) => scalar_out);

Within the component, the unconstrained ports will now appear to
have vector range (0 to 0).

The usual caveats apply concerning unconstrained ports
and synthesis.
--
Jonathan Bromley, Consultant

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