FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > VHDL

VHDL comp.lang.vhdl newsgroup / Usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 11-01-2003, 08:32 PM
ramzi
Guest
 
Posts: n/a
Default input file to static timing analysis

hi,

what's the informations needed for the static timing analysis (with
PrimeTime for example).

".blif" file for exemple, is it suffisant ? or I mast have the gates
delays labrary, and there's a timing calculation before the Analysis
starting ?

So is SDF file is suffisant in this case ?

thank you ....
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Static Timing Analysis Using Primetime for FPGAs [email protected] FPGA 13 08-03-2007 09:34 PM
Static Timing Analysis vs Dinamic Timing Analysis jajo FPGA 1 11-19-2006 03:17 AM
DDR SDRAM static timing analysis [email protected] FPGA 1 10-13-2006 06:24 PM
Jitter and Static Timing Analysis Jeremy Stringer FPGA 2 02-22-2005 12:51 AM
Static Timing Analysis Chris FPGA 0 07-30-2004 03:40 PM


All times are GMT +1. The time now is 02:48 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved