FPGA Central

I would like my testbench to be able to load data from text i/o into
two 1-d arrays of type real, of any length.

I looked through the text i/o example in "The Designer's Guide to Vhdl"
by Ashenden, but I'm still a little fuzzy.

I generated the data in exponential format in Matlab into a text file:

-3.295898437500E-003 4.272460937500E-003
.... ...


I would declare the two procedure output arrays in my signal list of my
test-bed. I then plan on looping through each value in the arrays every
clock cycle:

-- test bench architecture types,signals
type ARRAYOFREAL_T is array (natural range <>) of real;
signal real_stuff: ARRAYOFREAL_T(LENGTH-1 downto 0);
signal imag_stuff: ARRAYOFREAL_T(LENGTH-1 downto 0)

-- define the procedure as follows, but not sure how to write
-- coe_fn is the filename string
-- re, im are the arrays of real I want to contain the loaded values
procedure is load_coe_from file(coe_fn: in string;
re: out ARRAYOFREAL_T; im: out ARRAYOFREAL_T) is
....
begin
....

end procedure load_coe;

Any thoughts? Thanks.

Brandon wrote:
> I would like my testbench to be able to load data from text i/o into
> two 1-d arrays of type real, of any length.

> Any thoughts? Thanks.

Consider using vhdl constant arrays
instead of text i/o. This gives you
compile time and run time checks for free.

-- Mike Treseler

Well, the DUT is a filter, and I've already tested it with a general
constant array. Instead, I'm trying to get familiar with text i/o
because I would like my design to be able to load different coefficient
data from the text file. Depending on the application, it might be
necessary to change the coefficient set used by the filter.

For now, I'd like to just stick with one set of coefficients. The
test-bench would have a method to read the text file during
elaboration, parse through to get the values, and store them in a
constant array, which I can then access during my event process to load
the new filter coefficients.

Ok. Here is what I have inside my testbench entity, which I'm able to
compile. However, I am receiving an error when I try to load the
design. Note that the text file is located in the same directory as the
vhdl:

# Loading work.dut_tb(beh_ar)
# ** Error: (vsim-7) Failed to open VHDL file "cfir.coe" in rb mode.
# No such file or directory. (errno = ENOENT)
# Time: 0 ns Iteration: 0 Instance: /dut_tb

<SNIP>
....

-------------------------------------------------------------------------
-- load constant coefficient array process

-------------------------------------------------------------------------
load_coe: process
use std.textio.all;
file coe_file: text open read_mode is COE_FILE_NAME_C;

variable curLine_v : line;
variable curLineNum_v : natural := 0;
variable read_ok_v : boolean;
variable real_v : real;
variable imag_v : real;

begin
curLine_loop: while (curLineNum_v <= NUMTAPS_C-1) and
not (endfile(coe_file) ) loop
-- Read the current line
readline(coe_file,curLine_v);

-- Read real coefficient
read(curLine_v,real_v,read_ok_v);
if not read_ok_v then
report "fircplx_tb: Error reading real coefficient from line: "
& curLine_v.all
severity warning;
end if;

-- Read imag coefficient
read(curLine_v,imag_v,read_ok_v);
if not read_ok_v then
report "fircplx_tb: Error reading imag coefficient from line: "
& curLine_v.all
severity warning;
end if;

hre_array_s(curLineNum_v) <= real_v;
him_array_s(curLineNum_v) <= imag_v;
curLineNum_v := curLineNum_v+1;
next curLine_loop;
end loop curLine_loop;
wait;
end process load_coe;
end beh_ar;
</SNIP>

Brandon wrote:
> Well, the DUT is a filter, and I've already tested it with a general
> constant array. Instead, I'm trying to get familiar with text i/o
> because I would like my design to be able to load different coefficient
> data from the text file. Depending on the application, it might be
> necessary to change the coefficient set used by the filter.

I prefer to use an editor macro or other
script to convert text to vhdl constant format.
VHDL is excellent for hardware description
and simulation, but it far below average for
text processing and parsing.

-- Mike Treseler

Brandon wrote:
> Ok. Here is what I have inside my testbench entity, which I'm able to
> compile. However, I am receiving an error when I try to load the
> design. Note that the text file is located in the same directory as the
> vhdl:

Have your process write a test file and
see where it ends up. That's where cfir.coe
should be.

-- Mike Treseler